[llvm] r316822 - [X86] Use update_llc_test_checks.py to regenerate fast-isel-select-cmov2.ll
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 19:03:58 PDT 2017
Author: ctopper
Date: Fri Oct 27 19:03:58 2017
New Revision: 316822
URL: http://llvm.org/viewvc/llvm-project?rev=316822&view=rev
Log:
[X86] Use update_llc_test_checks.py to regenerate fast-isel-select-cmov2.ll
Modified:
llvm/trunk/test/CodeGen/X86/fast-isel-select-cmov2.ll
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-select-cmov2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-select-cmov2.ll?rev=316822&r1=316821&r2=316822&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-select-cmov2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-select-cmov2.ll Fri Oct 27 19:03:58 2017
@@ -1,188 +1,250 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; Test all the cmp predicates that can feed an integer conditional move.
define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_false_cmov
-; CHECK: movq %rsi, %rax
-; CHECK-NEXT: retq
+; CHECK-LABEL: select_fcmp_false_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: retq
%1 = fcmp false double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_oeq_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; SDAG-NEXT: cmovneq %rsi, %rdi
-; SDAG-NEXT: cmovpq %rsi, %rdi
-; SDAG-NEXT: movq %rdi, %rax
-; FAST-NEXT: setnp %al
-; FAST-NEXT: sete %cl
-; FAST-NEXT: testb %al, %cl
-; FAST-NEXT: cmoveq %rsi, %rdi
+; SDAG-LABEL: select_fcmp_oeq_cmov:
+; SDAG: ## BB#0:
+; SDAG-NEXT: ucomisd %xmm1, %xmm0
+; SDAG-NEXT: cmovneq %rsi, %rdi
+; SDAG-NEXT: cmovpq %rsi, %rdi
+; SDAG-NEXT: movq %rdi, %rax
+; SDAG-NEXT: retq
+;
+; FAST-LABEL: select_fcmp_oeq_cmov:
+; FAST: ## BB#0:
+; FAST-NEXT: ucomisd %xmm1, %xmm0
+; FAST-NEXT: setnp %al
+; FAST-NEXT: sete %cl
+; FAST-NEXT: testb %al, %cl
+; FAST-NEXT: cmoveq %rsi, %rdi
+; FAST-NEXT: movq %rdi, %rax
+; FAST-NEXT: retq
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ogt_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ogt_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovbeq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ogt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovbeq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ogt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_oge_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_oge_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovbq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_oge_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovbq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp oge double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_olt_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_olt_cmov
-; CHECK: ucomisd %xmm0, %xmm1
-; CHECK-NEXT: cmovbeq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_olt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbeq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp olt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ole_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ole_cmov
-; CHECK: ucomisd %xmm0, %xmm1
-; CHECK-NEXT: cmovbq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ole_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovbq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ole double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_one_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_one_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmoveq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_one_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmoveq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp one double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ord_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ord_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovpq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ord_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovpq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ord double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_uno_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_uno_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovnpq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_uno_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovnpq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp uno double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ueq_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ueq_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovneq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ueq_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovneq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ueq double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ugt_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ugt_cmov
-; CHECK: ucomisd %xmm0, %xmm1
-; CHECK-NEXT: cmovaeq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ugt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovaeq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_uge_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_uge_cmov
-; CHECK: ucomisd %xmm0, %xmm1
-; CHECK-NEXT: cmovaq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_uge_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+; CHECK-NEXT: cmovaq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp uge double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ult_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ult_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovaeq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ult_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovaeq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ult double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_ule_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: cmovaq %rsi, %rdi
+; CHECK-LABEL: select_fcmp_ule_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: cmovaq %rsi, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp ule double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_une_cmov
-; CHECK: ucomisd %xmm1, %xmm0
-; SDAG-NEXT: cmovneq %rdi, %rsi
-; SDAG-NEXT: cmovpq %rdi, %rsi
-; SDAG-NEXT: movq %rsi, %rax
-; FAST-NEXT: setp %al
-; FAST-NEXT: setne %cl
-; FAST-NEXT: orb %al, %cl
-; FAST-NEXT: cmoveq %rsi, %rdi
+; SDAG-LABEL: select_fcmp_une_cmov:
+; SDAG: ## BB#0:
+; SDAG-NEXT: ucomisd %xmm1, %xmm0
+; SDAG-NEXT: cmovneq %rdi, %rsi
+; SDAG-NEXT: cmovpq %rdi, %rsi
+; SDAG-NEXT: movq %rsi, %rax
+; SDAG-NEXT: retq
+;
+; FAST-LABEL: select_fcmp_une_cmov:
+; FAST: ## BB#0:
+; FAST-NEXT: ucomisd %xmm1, %xmm0
+; FAST-NEXT: setp %al
+; FAST-NEXT: setne %cl
+; FAST-NEXT: orb %al, %cl
+; FAST-NEXT: cmoveq %rsi, %rdi
+; FAST-NEXT: movq %rdi, %rax
+; FAST-NEXT: retq
%1 = fcmp une double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_fcmp_true_cmov(double %a, double %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_fcmp_true_cmov
-; CHECK: movq %rdi, %rax
+; CHECK-LABEL: select_fcmp_true_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
%1 = fcmp true double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_eq_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_eq_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovneq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_eq_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovneq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp eq i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_ne_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_ne_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmoveq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_ne_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmoveq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp ne i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_ugt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_ugt_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovbeq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_ugt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovbeq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp ugt i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -190,70 +252,84 @@ define i64 @select_icmp_ugt_cmov(i64 %a,
define i64 @select_icmp_uge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_uge_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovbq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_uge_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp uge i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_ult_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_ult_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovaeq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_ult_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovaeq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp ult i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_ule_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_ule_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovaq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_ule_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovaq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp ule i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_sgt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_sgt_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovleq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_sgt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovleq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp sgt i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_sge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_sge_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovlq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_sge_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovlq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp sge i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_slt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_slt_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovgeq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_slt_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovgeq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp slt i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
}
define i64 @select_icmp_sle_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
-; CHECK-LABEL: select_icmp_sle_cmov
-; CHECK: cmpq %rsi, %rdi
-; CHECK-NEXT: cmovgq %rcx, %rdx
-; CHECK-NEXT: movq %rdx, %rax
+; CHECK-LABEL: select_icmp_sle_cmov:
+; CHECK: ## BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: cmovgq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
%1 = icmp sle i64 %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
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