[PATCH] D39350: AMDGPU: Add CPUCoherentL2 feature

[Tony Tye via Phabricator via llvm-commits]

t-tye added a comment.

In https://reviews.llvm.org/D39350#909426, @jvesely wrote:

> In https://reviews.llvm.org/D39350#908697, @kzhuravl wrote:
>
> > Is it going to be used with amdhsa os? Where can I find the spec for this?
>
>
> I planned to use this to enable system level atomics that work between CPU and dGPU. atm it only works on kaveri/carrizo.
>
> In https://reviews.llvm.org/D39350#908854, @t-tye wrote:
>
> > Are we sure using SLC is the way to achieve this? IIRC SLC can be used for streaming, but does not ensure L2 bypass. On an APU the MTYPE=CC specifies the memory policy that support coherence.
>
>
> The CI and GCN3 ISA specs for SLC say: "System Level Coherent. When set, accesses are forced to miss in level 2 texture cache and are coherent with system memory."
>  Has this been changed?
>  I only found MTYPE references to for image and buffer rsrc, is there a way to set it for flat ops?
>  The ISA specs also don't mention what values are allowed in those 3 bits.


I do not think using SLC will achieve what you are looking for. The default memory policies for SLC are to enable STREAMING mode which leaves cache lines in the L2 cache and so will not achieve coherence. What you need is for the L2 cache to be kept coherent with the memory fabric which is what the MTYPE and IOMMUv2 can provide on APUs. The runtime can configure the hardware to do this. Buffer instructions use V# that can specify the MTYPE, and there are configuration registers that can be set for each aperture with the MTYPE to use.

What runtime are you intending to use to load and execute the code produced?

How where you thinking of controlling when to enable this as you would not want to affect the existing code generated as adding SLC will make code execute less performantly?


Repository:
  rL LLVM

https://reviews.llvm.org/D39350