[llvm] r316771 - [X86][F16C] Fix btver2 AGU pipe scheduling

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Oct 27 09:34:58 2017
New Revision: 316771

URL: http://llvm.org/viewvc/llvm-project?rev=316771&view=rev
Log:
[X86][F16C] Fix btver2 AGU pipe scheduling

Use the store AGU for stores, and the load AGU needs to be the first pipe for loads

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=316771&r1=316770&r2=316771&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Fri Oct 27 09:34:58 2017
@@ -428,13 +428,13 @@ def WriteCVT3: SchedWriteRes<[JFPU1]> {
 def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
 def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
 
-def WriteCVT3St: SchedWriteRes<[JFPU1, JLAGU]> {
+def WriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> {
   let Latency = 3;
   let ResourceCycles = [1, 1];
 }
 def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
 
-def WriteCVT3Ld: SchedWriteRes<[JFPU1, JLAGU]> {
+def WriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> {
   let Latency = 8;
   let ResourceCycles = [1, 1];
 }
@@ -447,7 +447,7 @@ def WriteCVTPS2PHY: SchedWriteRes<[JFPU1
 }
 def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
 
-def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JLAGU]> {
+def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> {
   let Latency = 11;
   let ResourceCycles = [2,2,1];
   let NumMicroOps = 3;