[PATCH] D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain.

Jun Ryung Ju via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 26 18:10:10 PDT 2017


junryoungju added inline comments.


================
Comment at: test/Analysis/ScalarEvolution/cond_1.ll:15
+  %inc = zext i1 %cmp to i32
+  %inc.start.0 = add nsw i32 %start.0, %inc
+  br i1 %cmp, label %do.body, label %do.end
----------------
sanjoy wrote:
> I thought @jbhateja 's patch should already get cases like these?  If you care about switch instructions, you probably need to add support for switches to the rewriter he's written (it already supports select).
That isn't really support the select instruction.
I think you should try cond_3.ll for it.

also, that patch doesn't generates correct clang assemblies. (not emitting optimized assemblies)
please check that @jbhateja 's patch is "really" supporting a select or icmp instruction.

and I don't think that rewriting for these works ins't really good idea.
because almost all visitors will register SCEVs on value map, (SCEVCallbackVM)
remember the first goal, its not evolution a ICmp or Select instruction on createAddRecFromPHI
we do not need to rewrite it if we are going to evolute it, we are just check that "condition" is actually true or false on now.

if we are going to evolute it or visiting it. we just need to create a SCEVConditional, just analyze backend taken count dynamically.
just comparing each step.


now I am going to talking about switch instruction.
if we are not handling it as a "evolution" I am just going to check that switch has like step. 
like this
```
switch(step)
{
    case 0: step++;
    case 1: step++;
    case 2: step++;
    case 3: break;
}
```

or not, I am just going to create SCEVConditional for dynamic analyize.


https://reviews.llvm.org/D37660





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