[llvm] r316388 - [GISel][ARM]: Fix illegal Generic copies in tests
Aditya Nandakumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 15:53:08 PDT 2017
Author: aditya_nandakumar
Date: Mon Oct 23 15:53:08 2017
New Revision: 316388
URL: http://llvm.org/viewvc/llvm-project?rev=316388&view=rev
Log:
[GISel][ARM]: Fix illegal Generic copies in tests
This is in preparation for a verifier check that makes sure
copies are of the same size (when generic virtual registers are involved).
Modified:
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=316388&r1=316387&r2=316388&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Mon Oct 23 15:53:08 2017
@@ -1,13 +1,11 @@
# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
- define void @test_zext_s1() { ret void }
- define void @test_sext_s1() { ret void }
- define void @test_sext_s8() { ret void }
- define void @test_zext_s16() { ret void }
- define void @test_anyext_s8() { ret void }
- define void @test_anyext_s16() { ret void }
-
- define void @test_trunc_s32_16() { ret void }
+ define void @test_trunc_and_zext_s1() { ret void }
+ define void @test_trunc_and_sext_s1() { ret void }
+ define void @test_trunc_and_sext_s8() { ret void }
+ define void @test_trunc_and_zext_s16() { ret void }
+ define void @test_trunc_and_anyext_s8() { ret void }
+ define void @test_trunc_and_anyext_s16() { ret void }
define void @test_add_s32() { ret void }
@@ -52,8 +50,8 @@
attributes #2 = { "target-features"="+hwdiv-arm" }
...
---
-name: test_zext_s1
-# CHECK-LABEL: name: test_zext_s1
+name: test_trunc_and_zext_s1
+# CHECK-LABEL: name: test_trunc_and_zext_s1
legalized: true
regBankSelected: true
selected: false
@@ -61,25 +59,29 @@ selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
+ - { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
- %0(s1) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
- %1(s32) = G_ZEXT %0(s1)
- ; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
+ %1(s1) = G_TRUNC %0(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
- %r0 = COPY %1(s32)
+ %2(s32) = G_ZEXT %1(s1)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGTRUNC]], 1, 14, _, _
+
+ %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
-name: test_sext_s1
-# CHECK-LABEL: name: test_sext_s1
+name: test_trunc_and_sext_s1
+# CHECK-LABEL: name: test_trunc_and_sext_s1
legalized: true
regBankSelected: true
selected: false
@@ -92,22 +94,25 @@ body: |
bb.0:
liveins: %r0
- %0(s1) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
- %1(s32) = G_SEXT %0(s1)
- ; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
+ %1(s1) = G_TRUNC %0(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+
+ %2(s32) = G_SEXT %1(s1)
+ ; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGTRUNC]], 1, 14, _, _
; CHECK: [[VREGEXT:%[0-9]+]] = RSBri [[VREGAND]], 0, 14, _, _
- %r0 = COPY %1(s32)
+ %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
-name: test_sext_s8
-# CHECK-LABEL: name: test_sext_s8
+name: test_trunc_and_sext_s8
+# CHECK-LABEL: name: test_trunc_and_sext_s8
legalized: true
regBankSelected: true
selected: false
@@ -115,51 +120,29 @@ selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
+ - { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
- %0(s8) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
- %1(s32) = G_SEXT %0(s8)
- ; CHECK: [[VREGEXT:%[0-9]+]] = SXTB [[VREGX]], 0, 14, _
-
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
-
- BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
-...
----
-name: test_zext_s16
-# CHECK-LABEL: name: test_zext_s16
-legalized: true
-regBankSelected: true
-selected: false
-# CHECK: selected: true
-registers:
- - { id: 0, class: gprb }
- - { id: 1, class: gprb }
-body: |
- bb.0:
- liveins: %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
- %0(s16) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
- %1(s32) = G_ZEXT %0(s16)
- ; CHECK: [[VREGEXT:%[0-9]+]] = UXTH [[VREGX]], 0, 14, _
+ %2(s32) = G_SEXT %1(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = SXTB [[VREGTRUNC]], 0, 14, _
- %r0 = COPY %1(s32)
+ %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
-name: test_anyext_s8
-# CHECK-LABEL: name: test_anyext_s8
+name: test_trunc_and_zext_s16
+# CHECK-LABEL: name: test_trunc_and_zext_s16
legalized: true
regBankSelected: true
selected: false
@@ -167,25 +150,29 @@ selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
+ - { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
- %0(s8) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
- %1(s32) = G_ANYEXT %0(s8)
- ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
+ %1(s16) = G_TRUNC %0(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
- %r0 = COPY %1(s32)
+ %2(s32) = G_ZEXT %1(s16)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = UXTH [[VREGTRUNC]], 0, 14, _
+
+ %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
-name: test_anyext_s16
-# CHECK-LABEL: name: test_anyext_s16
+name: test_trunc_and_anyext_s8
+# CHECK-LABEL: name: test_trunc_and_anyext_s8
legalized: true
regBankSelected: true
selected: false
@@ -193,25 +180,29 @@ selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
+ - { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
- %0(s16) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+
+ %1(s8) = G_TRUNC %0(s32)
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
- %1(s32) = G_ANYEXT %0(s16)
- ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
+ %2(s32) = G_ANYEXT %1(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGTRUNC]]
- %r0 = COPY %1(s32)
+ %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
-name: test_trunc_s32_16
-# CHECK-LABEL: name: test_trunc_s32_16
+name: test_trunc_and_anyext_s16
+# CHECK-LABEL: name: test_trunc_and_anyext_s16
legalized: true
regBankSelected: true
selected: false
@@ -219,20 +210,22 @@ selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
-# CHECK-DAG: id: 0, class: gpr
-# CHECK-DAG: id: 1, class: gpr
+ - { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+ ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
%1(s16) = G_TRUNC %0(s32)
- ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREGX]]
+ ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
- %r0 = COPY %1(s16)
- ; CHECK: %r0 = COPY [[VREGTRUNC]]
+ %2(s32) = G_ANYEXT %1(s16)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGTRUNC]]
+
+ %r0 = COPY %2(s32)
+ ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -711,10 +704,12 @@ registers:
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
+ - { id: 4, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
# CHECK-DAG: id: 3, class: gpr
+# CHECK-DAG: id: 4, class: gpr
fixedStack:
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
@@ -740,8 +735,11 @@ body: |
%3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: [[LD1VREG:%[0-9]+]] = LDRBi12 [[FI1VREG]], 0, 14, _
- %r0 = COPY %3
- ; CHECK: %r0 = COPY [[LD1VREG]]
+ %4(s32) = G_ANYEXT %3(s1)
+ ; CHECK: [[RES:%[0-9]+]] = COPY [[LD1VREG]]
+
+ %r0 = COPY %4
+ ; CHECK: %r0 = COPY [[RES]]
BX_RET 14, _
; CHECK: BX_RET 14, _
@@ -822,14 +820,14 @@ registers:
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: %r0, %r1, %s0, %d0
%0(p0) = COPY %r0
- %1(s8) = COPY %r3
- %2(s16) = COPY %r2
%3(s32) = COPY %r1
%4(s32) = COPY %s0
%5(s64) = COPY %d2
+ %1(s8) = G_TRUNC %3(s32)
+ %2(s16) = G_TRUNC %3(s32)
G_STORE %1(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
@@ -927,7 +925,7 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
@@ -935,8 +933,8 @@ body: |
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s1) = COPY %r2
- ; CHECK: [[VREGC:%[0-9]+]] = COPY %r2
+ %2(s1) = G_TRUNC %1(s32)
+ ; CHECK: [[VREGC:%[0-9]+]] = COPY [[VREGY]]
%3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
@@ -962,7 +960,7 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: %r0, %r1
%0(p0) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
@@ -970,8 +968,8 @@ body: |
%1(p0) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s1) = COPY %r2
- ; CHECK: [[VREGC:%[0-9]+]] = COPY %r2
+ %2(s1) = G_TRUNC %1(p0)
+ ; CHECK: [[VREGC:%[0-9]+]] = COPY [[VREGY]]
%3(p0) = G_SELECT %2(s1), %0, %1
; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
@@ -992,16 +990,19 @@ selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
+ - { id: 1, class: gprb }
body: |
bb.0:
; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %r0
- %0(s1) = COPY %r0
- ; CHECK: [[COND:%[0-9]+]] = COPY %r0
+ %0(s32) = COPY %r0
+ ; CHECK: [[COND32:%[0-9]+]] = COPY %r0
+ %1(s1) = G_TRUNC %0(s32)
+ ; CHECK: [[COND:%[0-9]+]] = COPY [[COND32]]
- G_BRCOND %0(s1), %bb.1
+ G_BRCOND %1(s1), %bb.1
; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr
; CHECK: Bcc %bb.1, 0, %cpsr
G_BR %bb.2
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir?rev=316388&r1=316387&r2=316388&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir Mon Oct 23 15:53:08 2017
@@ -105,16 +105,29 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16)
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
@@ -126,11 +139,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
- ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R16]]
; SOFT-NOT: G_SDIV
- %2(s16) = G_SDIV %0, %1
+ %4(s16) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s16)
+ %5(s32) = G_SEXT %4(s16)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -145,16 +160,27 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16)
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
@@ -166,11 +192,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
- ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R16]]
; SOFT-NOT: G_UDIV
- %2(s16) = G_UDIV %0, %1
+ %4(s16) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s16)
+ %5(s32) = G_ZEXT %4(s16)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -185,16 +213,29 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8)
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
@@ -206,11 +247,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
- ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R8]]
; SOFT-NOT: G_SDIV
- %2(s8) = G_SDIV %0, %1
+ %4(s8) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s8)
+ %5(s32) = G_SEXT %4(s8)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -225,16 +268,27 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8)
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
@@ -246,11 +300,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
- ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R8]]
; SOFT-NOT: G_UDIV
- %2(s8) = G_UDIV %0, %1
+ %4(s8) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s8)
+ %5(s32) = G_ZEXT %4(s8)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -341,16 +397,29 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16)
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
@@ -364,11 +433,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
- ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R16]]
; SOFT-NOT: G_SREM
- %2(s16) = G_SREM %0, %1
+ %4(s16) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s16)
+ %5(s32) = G_SEXT %4(s16)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -383,16 +454,27 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16)
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
@@ -406,11 +488,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
- ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R16]]
; SOFT-NOT: G_UREM
- %2(s16) = G_UREM %0, %1
+ %4(s16) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s16)
+ %5(s32) = G_ZEXT %4(s16)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -425,16 +509,29 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8)
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
@@ -448,11 +545,13 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
- ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R8]]
; SOFT-NOT: G_SREM
- %2(s8) = G_SREM %0, %1
+ %4(s8) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s8)
+ %5(s32) = G_SEXT %4(s8)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -467,16 +566,27 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
- ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8)
- ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8)
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
+ ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+ ; The G_TRUNC will combine with the extensions introduced by the legalizer,
+ ; leading to the following complicated sequences.
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
+ ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
+ ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
+ ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
+ ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
+ ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+ %0(s32) = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s32) = COPY %r1
+ %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
@@ -490,10 +600,12 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
- ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
+ ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R8]]
; SOFT-NOT: G_UREM
- %2(s8) = G_UREM %0, %1
+ %4(s8) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s8)
+ %5(s32) = G_ZEXT %4(s8)
+ %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=316388&r1=316387&r2=316388&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Mon Oct 23 15:53:08 2017
@@ -71,7 +71,7 @@ body: |
bb.0:
liveins: %r0
- %0(s8) = COPY %r0
+ %0(s8) = G_CONSTANT i8 42
%1(s32) = G_SEXT %0
; G_SEXT with s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_SEXT {{%[0-9]+}}
@@ -93,7 +93,7 @@ body: |
bb.0:
liveins: %r0
- %0(s16) = COPY %r0
+ %0(s16) = G_CONSTANT i16 42
%1(s32) = G_ZEXT %0
; G_ZEXT with s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_ZEXT {{%[0-9]+}}
@@ -112,18 +112,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 12
+ %1(s8) = G_CONSTANT i8 30
%2(s8) = G_ADD %0, %1
; G_ADD with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -138,18 +140,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 32
+ %1(s16) = G_CONSTANT i16 10
%2(s16) = G_ADD %0, %1
; G_ADD with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -190,18 +194,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 48
+ %1(s8) = G_CONSTANT i8 6
%2(s8) = G_SUB %0, %1
; G_SUB with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -216,18 +222,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 58
+ %1(s16) = G_CONSTANT i16 16
%2(s16) = G_SUB %0, %1
; G_SUB with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -268,18 +276,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 7
+ %1(s8) = G_CONSTANT i8 6
%2(s8) = G_MUL %0, %1
; G_MUL with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -294,18 +304,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 3
+ %1(s16) = G_CONSTANT i16 14
%2(s16) = G_MUL %0, %1
; G_MUL with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -346,18 +358,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 46
+ %1(s8) = G_CONSTANT i8 58
%2(s8) = G_AND %0, %1
; G_AND with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -372,18 +386,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 43
+ %1(s16) = G_CONSTANT i16 106
%2(s16) = G_AND %0, %1
; G_AND with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -424,18 +440,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 32
+ %1(s8) = G_CONSTANT i8 10
%2(s8) = G_OR %0, %1
; G_OR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -450,18 +468,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 34
+ %1(s16) = G_CONSTANT i16 10
%2(s16) = G_OR %0, %1
; G_OR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -502,18 +522,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 10
+ %1(s8) = G_CONSTANT i8 32
%2(s8) = G_XOR %0, %1
; G_XOR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s8)
+ %3(s32) = G_SEXT %2(s8)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -528,18 +550,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 40
+ %1(s16) = G_CONSTANT i16 2
%2(s16) = G_XOR %0, %1
; G_XOR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s16)
+ %3(s32) = G_SEXT %2(s16)
+ %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
@@ -740,11 +764,11 @@ body: |
G_STORE %1(s64), %0(p0) :: (store 8)
%2(s32) = COPY %r2
G_STORE %2(s32), %0(p0) :: (store 4)
- %3(s16) = COPY %r3
+ %3(s16) = G_CONSTANT i16 42
G_STORE %3(s16), %0(p0) :: (store 2)
- %4(s8) = COPY %r4
+ %4(s8) = G_CONSTANT i8 21
G_STORE %4(s8), %0(p0) :: (store 1)
- %5(s1) = COPY %r5
+ %5(s1) = G_CONSTANT i1 1
G_STORE %5(s1), %0(p0) :: (store 1)
%6(p0) = COPY %r6
G_STORE %6(p0), %0(p0) :: (store 4)
@@ -831,8 +855,8 @@ body: |
bb.0:
liveins: %r0, %r1
- %0(s8) = COPY %r0
- %1(s8) = COPY %r1
+ %0(s8) = G_CONSTANT i8 42
+ %1(s8) = G_CONSTANT i8 43
%2(s1) = G_ICMP intpred(ne), %0(s8), %1
; G_ICMP with s8 should widen
; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
@@ -858,8 +882,8 @@ body: |
bb.0:
liveins: %r0, %r1
- %0(s16) = COPY %r0
- %1(s16) = COPY %r1
+ %0(s16) = G_CONSTANT i16 42
+ %1(s16) = G_CONSTANT i16 46
%2(s1) = G_ICMP intpred(slt), %0(s16), %1
; G_ICMP with s16 should widen
; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
@@ -913,7 +937,7 @@ body: |
%0(s32) = COPY %r0
%1(s32) = COPY %r1
- %2(s1) = COPY %r2
+ %2(s1) = G_CONSTANT i1 1
%3(s32) = G_SELECT %2(s1), %0, %1
; G_SELECT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
@@ -939,7 +963,7 @@ body: |
%0(p0) = COPY %r0
%1(p0) = COPY %r1
- %2(s1) = COPY %r2
+ %2(s1) = G_CONSTANT i1 0
%3(p0) = G_SELECT %2(s1), %0, %1
; G_SELECT with p0 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=316388&r1=316387&r2=316388&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Mon Oct 23 15:53:08 2017
@@ -395,15 +395,15 @@ registers:
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3, %r4, %r5, %d6
+ liveins: %r0, %r1, %r5, %d6
%0(p0) = COPY %r0
%1(s32) = COPY %r1
G_STORE %1(s32), %0 :: (store 4)
- %2(s16) = COPY %r2
+ %2(s16) = G_TRUNC %1(s32)
G_STORE %2(s16), %0 :: (store 2)
- %3(s8) = COPY %r3
+ %3(s8) = G_TRUNC %1(s32)
G_STORE %3(s8), %0 :: (store 1)
- %4(s1) = COPY %r4
+ %4(s1) = G_TRUNC %1(s32)
G_STORE %4(s1), %0 :: (store 1)
%5(p0) = COPY %r5
G_STORE %5(p0), %0 :: (store 4)
@@ -511,16 +511,19 @@ selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.0:
liveins: %r0
- %0(s8) = COPY %r0
- %1(s32) = G_ANYEXT %0(s8)
- %r0 = COPY %1(s32)
+ %0(s32) = COPY %r0
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s32) = G_ANYEXT %1(s8)
+ %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -532,16 +535,19 @@ selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.0:
liveins: %r0
- %0(s16) = COPY %r0
- %1(s32) = G_ANYEXT %0(s16)
- %r0 = COPY %1(s32)
+ %0(s32) = COPY %r0
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s32) = G_ANYEXT %1(s16)
+ %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
@@ -553,17 +559,20 @@ selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: %r0, %r1
%0(s32) = COPY %r0
+ %2(p0) = COPY %r1
%1(s16) = G_TRUNC %0(s32)
- %r0 = COPY %1(s16)
- BX_RET 14, _, implicit %r0
+ G_STORE %1(s16), %2 :: (store 2)
+ BX_RET 14, _
...
---
name: test_icmp_eq_s32
@@ -575,6 +584,7 @@ selected: false
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@@ -603,6 +613,7 @@ selected: false
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@@ -631,6 +642,7 @@ selected: false
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+# CHECK: - { id: 3, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@@ -660,21 +672,24 @@ selected: false
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
+# CHECK: - { id: 4, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
+ - { id: 4, class: _ }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
- %2(s1) = COPY %r2
- %3(s32) = G_SELECT %2(s1), %0, %1
- %r0 = COPY %3(s32)
+ %2(s32) = COPY %r2
+ %3(s1) = G_TRUNC %2(s32)
+ %4(s32) = G_SELECT %3(s1), %0, %1
+ %r0 = COPY %4(s32)
BX_RET 14, _, implicit %r0
...
@@ -687,7 +702,9 @@ regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
+ - { id: 1, class: _ }
# CHECK: { id: 0, class: gprb, preferred-register: '' }
+# CHECK: { id: 1, class: gprb, preferred-register: '' }
# Check that we map the condition of the G_BRCOND into the GPR.
# For the G_BR, there are no registers to map, but make sure we don't crash.
body: |
@@ -695,8 +712,9 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %r0
- %0(s1) = COPY %r0
- G_BRCOND %0(s1), %bb.1
+ %0(s32) = COPY %r0
+ %1(s1) = G_TRUNC %0(s32)
+ G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
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