[PATCH] D39193: [ARM] Don't omit non-default predication code

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

This was causing the (invalid) predicated versions of the NEON VRINTX and VRINTZ instructions to be accepted, with the condition code being ignored.

Also, there is no NEON VRINTR instruction, so that part of the check was not necessary.


Repository:
  rL LLVM

https://reviews.llvm.org/D39193

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/invalid-fp-armv8.s
  test/MC/ARM/invalid-neon-v8.s


Index: test/MC/ARM/invalid-neon-v8.s
===================================================================
--- test/MC/ARM/invalid-neon-v8.s
+++ test/MC/ARM/invalid-neon-v8.s
@@ -72,3 +72,9 @@
 @ CHECK: error: operand must be a register in range [q0, q15]
 vmullge.p64 q0, d16, d17
 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
+
+// These instructions are predicable in VFP but not in NEON
+vrintzeq.f32 d0, d1
+vrintxgt.f32 d0, d1
+@ CHECK: error: invalid operand for instruction
+@ CHECK: error: invalid operand for instruction
Index: test/MC/ARM/invalid-fp-armv8.s
===================================================================
--- test/MC/ARM/invalid-fp-armv8.s
+++ test/MC/ARM/invalid-fp-armv8.s
@@ -81,7 +81,7 @@
 vrintrlo.f32.f32 d3, q0
 @ V8: error: invalid operands for instruction
 vrintxcs.f32.f32 d3, d0
-@ V8: error: instruction requires: NEON
+@ V8: error: invalid operands for instruction
 
 vrinta.f64.f64 s3, q0
 @ V8: error: invalid operands for instruction
Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5809,7 +5809,7 @@
                                               OperandVector &Operands) {
   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
   unsigned RegIdx = 3;
-  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
+  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") &&
       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
@@ -6104,7 +6104,8 @@
   // Some instructions have the same mnemonic, but don't always
   // have a predicate. Distinguish them here and delete the
   // predicate if needed.
-  if (shouldOmitPredicateOperand(Mnemonic, Operands))
+  if (PredicationCode == ARMCC::AL &&
+      shouldOmitPredicateOperand(Mnemonic, Operands))
     Operands.erase(Operands.begin() + 1);
 
   // ARM mode 'blx' need special handling, as the register operand version


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