[llvm] r316345 - [X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 09:49:26 PDT 2017
Author: ctopper
Date: Mon Oct 23 09:49:26 2017
New Revision: 316345
URL: http://llvm.org/viewvc/llvm-project?rev=316345&view=rev
Log:
[X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
Modified:
llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
llvm/trunk/utils/TableGen/X86DisassemblerTables.h
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=316345&r1=316344&r2=316345&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Mon Oct 23 09:49:26 2017
@@ -74,7 +74,7 @@ static inline const char* stringForOpera
/// @param parent - The class that may be the superset
/// @return - True if child is a subset of parent, false otherwise.
static inline bool inheritsFrom(InstructionContext child,
- InstructionContext parent,
+ InstructionContext parent, bool noPrefix = true,
bool VEX_LIG = false, bool VEX_WIG = false,
bool AdSize64 = false) {
if (child == parent)
@@ -83,25 +83,25 @@ static inline bool inheritsFrom(Instruct
switch (parent) {
case IC:
return(inheritsFrom(child, IC_64BIT, AdSize64) ||
- inheritsFrom(child, IC_OPSIZE) ||
+ (noPrefix && inheritsFrom(child, IC_OPSIZE, noPrefix)) ||
inheritsFrom(child, IC_ADSIZE) ||
- inheritsFrom(child, IC_XD) ||
- inheritsFrom(child, IC_XS));
+ (noPrefix && inheritsFrom(child, IC_XD, noPrefix)) ||
+ (noPrefix && inheritsFrom(child, IC_XS, noPrefix)));
case IC_64BIT:
return(inheritsFrom(child, IC_64BIT_REXW) ||
- inheritsFrom(child, IC_64BIT_OPSIZE) ||
+ (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE, noPrefix)) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
- inheritsFrom(child, IC_64BIT_XD) ||
- inheritsFrom(child, IC_64BIT_XS));
+ (noPrefix && inheritsFrom(child, IC_64BIT_XD, noPrefix)) ||
+ (noPrefix && inheritsFrom(child, IC_64BIT_XS, noPrefix)));
case IC_OPSIZE:
return inheritsFrom(child, IC_64BIT_OPSIZE) ||
inheritsFrom(child, IC_OPSIZE_ADSIZE);
case IC_ADSIZE:
- return inheritsFrom(child, IC_OPSIZE_ADSIZE);
+ return (noPrefix && inheritsFrom(child, IC_OPSIZE_ADSIZE, noPrefix));
case IC_OPSIZE_ADSIZE:
return false;
case IC_64BIT_ADSIZE:
- return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
+ return (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE, noPrefix));
case IC_64BIT_OPSIZE_ADSIZE:
return false;
case IC_XD:
@@ -113,9 +113,9 @@ static inline bool inheritsFrom(Instruct
case IC_XS_OPSIZE:
return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
case IC_64BIT_REXW:
- return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
- inheritsFrom(child, IC_64BIT_REXW_XD) ||
- inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
+ return((noPrefix && inheritsFrom(child, IC_64BIT_REXW_XS, noPrefix)) ||
+ (noPrefix && inheritsFrom(child, IC_64BIT_REXW_XD, noPrefix)) ||
+ (noPrefix && inheritsFrom(child, IC_64BIT_REXW_OPSIZE, noPrefix)) ||
(!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
case IC_64BIT_OPSIZE:
return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
@@ -1108,6 +1108,7 @@ void DisassemblerTables::setTableFields(
const ModRMFilter &filter,
InstrUID uid,
bool is32bit,
+ bool noPrefix,
bool ignoresVEX_L,
bool ignoresVEX_W,
unsigned addressSize) {
@@ -1120,8 +1121,8 @@ void DisassemblerTables::setTableFields(
bool adSize64 = addressSize == 64;
if (inheritsFrom((InstructionContext)index,
- InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
- ignoresVEX_W, adSize64))
+ InstructionSpecifiers[uid].insnContext, noPrefix,
+ ignoresVEX_L, ignoresVEX_W, adSize64))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
filter,
uid,
Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.h?rev=316345&r1=316344&r2=316345&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.h (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.h Mon Oct 23 09:49:26 2017
@@ -244,6 +244,7 @@ public:
/// correspond to the desired instruction.
/// @param uid - The unique ID of the instruction.
/// @param is32bit - Instructon is only 32-bit
+ /// @param noPrefix - Instruction record has no prefix.
/// @param ignoresVEX_L - Instruction ignores VEX.L
/// @param ignoresVEX_W - Instruction ignores VEX.W
/// @param AddrSize - Instructions address size 16/32/64. 0 is unspecified
@@ -253,6 +254,7 @@ public:
const ModRMFilter &filter,
InstrUID uid,
bool is32bit,
+ bool noPrefix,
bool ignoresVEX_L,
bool ignoresVEX_W,
unsigned AddrSize);
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=316345&r1=316344&r2=316345&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Oct 23 09:49:26 2017
@@ -800,11 +800,12 @@ void RecognizableInstr::emitDecodePath(D
currentOpcode < opcodeToSet + 8;
++currentOpcode)
tables.setTableFields(opcodeType, insnContext(), currentOpcode, *filter,
- UID, Is32Bit, IgnoresVEX_L || EncodeRC,
+ UID, Is32Bit, OpPrefix == 0,
+ IgnoresVEX_L || EncodeRC,
VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
} else {
tables.setTableFields(opcodeType, insnContext(), opcodeToSet, *filter, UID,
- Is32Bit, IgnoresVEX_L || EncodeRC,
+ Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
}
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