[llvm] r316336 - [X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 09:00:58 PDT 2017
Author: rksimon
Date: Mon Oct 23 09:00:57 2017
New Revision: 316336
URL: http://llvm.org/viewvc/llvm-project?rev=316336&view=rev
Log:
[X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.
Remove AssertZext and instead add PEXTRW/PEXTRB support to computeKnownBitsForTargetNode to simplify instruction selection.
Differential Revision: https://reviews.llvm.org/D39169
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=316336&r1=316335&r2=316336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 23 09:00:57 2017
@@ -5931,19 +5931,13 @@ static bool getFauxShuffleMask(SDValue N
SDValue N0 = N.getOperand(0);
SDValue SrcExtract;
- if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
- N0.getOperand(0).getValueType() == VT) {
+ if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+ N0.getOperand(0).getValueType() == VT) ||
+ (N0.getOpcode() == X86ISD::PEXTRW &&
+ N0.getOperand(0).getValueType() == MVT::v8i16) ||
+ (N0.getOpcode() == X86ISD::PEXTRB &&
+ N0.getOperand(0).getValueType() == MVT::v16i8)) {
SrcExtract = N0;
- } else if (N0.getOpcode() == ISD::AssertZext &&
- N0.getOperand(0).getOpcode() == X86ISD::PEXTRW &&
- cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i16) {
- SrcExtract = N0.getOperand(0);
- assert(SrcExtract.getOperand(0).getValueType() == MVT::v8i16);
- } else if (N0.getOpcode() == ISD::AssertZext &&
- N0.getOperand(0).getOpcode() == X86ISD::PEXTRB &&
- cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i8) {
- SrcExtract = N0.getOperand(0);
- assert(SrcExtract.getOperand(0).getValueType() == MVT::v16i8);
}
if (!SrcExtract || !isa<ConstantSDNode>(SrcExtract.getOperand(1)))
@@ -5979,16 +5973,15 @@ static bool getFauxShuffleMask(SDValue N
return true;
}
- // Attempt to recognise a PINSR*(ASSERTZEXT(PEXTR*)) shuffle pattern.
+ // Attempt to recognise a PINSR*(PEXTR*) shuffle pattern.
// TODO: Expand this to support INSERT_VECTOR_ELT/etc.
unsigned ExOp =
(X86ISD::PINSRB == Opcode ? X86ISD::PEXTRB : X86ISD::PEXTRW);
- if (InScl.getOpcode() != ISD::AssertZext ||
- InScl.getOperand(0).getOpcode() != ExOp)
+ if (InScl.getOpcode() != ExOp)
return false;
- SDValue ExVec = InScl.getOperand(0).getOperand(0);
- uint64_t ExIdx = InScl.getOperand(0).getConstantOperandVal(1);
+ SDValue ExVec = InScl.getOperand(0);
+ uint64_t ExIdx = InScl.getConstantOperandVal(1);
assert(ExIdx < NumElts && "Illegal extraction index");
Ops.push_back(InVec);
Ops.push_back(ExVec);
@@ -14186,9 +14179,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT_S
if (VT.getSizeInBits() == 8) {
SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
- DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Extract);
}
if (VT == MVT::f32) {
@@ -14347,9 +14338,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
// Transform it so it match pextrw which produces a 32-bit result.
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
- DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Extract);
}
if (Subtarget.hasSSE41())
@@ -27155,6 +27144,17 @@ void X86TargetLowering::computeKnownBits
Known.Zero.setBitsFrom(NumLoBits);
break;
}
+ case X86ISD::PEXTRB:
+ case X86ISD::PEXTRW: {
+ SDValue Src = Op.getOperand(0);
+ EVT SrcVT = Src.getValueType();
+ APInt DemandedElt = APInt::getOneBitSet(SrcVT.getVectorNumElements(),
+ Op.getConstantOperandVal(1));
+ DAG.computeKnownBits(Src, Known, DemandedElt, Depth + 1);
+ Known = Known.zextOrTrunc(BitWidth);
+ Known.Zero.setBitsFrom(SrcVT.getScalarSizeInBits());
+ break;
+ }
case X86ISD::VSHLI:
case X86ISD::VSRLI: {
if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
@@ -30082,9 +30082,7 @@ static SDValue combineExtractWithShuffle
unsigned OpCode = (SrcVT == MVT::v8i16 ? X86ISD::PEXTRW : X86ISD::PEXTRB);
SDValue ExtOp = DAG.getNode(OpCode, dl, MVT::i32, SrcOp,
DAG.getIntPtrConstant(SrcIdx, dl));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, ExtOp,
- DAG.getValueType(SrcSVT));
- return DAG.getZExtOrTrunc(Assert, dl, VT);
+ return DAG.getZExtOrTrunc(ExtOp, dl, VT);
}
return SDValue();
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=316336&r1=316335&r2=316336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Oct 23 09:00:57 2017
@@ -9163,9 +9163,8 @@ multiclass avx512_extract_elt_bw_m<bits<
def mr : AVX512Ii8<opc, MRMDestMem, (outs),
(ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
- imm:$src2)))),
- addr:$dst)]>,
+ [(store (_.EltVT (trunc (OpNode (_.VT _.RC:$src1), imm:$src2))),
+ addr:$dst)]>,
EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
}
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=316336&r1=316335&r2=316336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Oct 23 09:00:57 2017
@@ -5529,8 +5529,8 @@ multiclass SS41I_extract8<bits<8> opc, s
(ins i8mem:$dst, VR128:$src1, u8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
- imm:$src2)))), addr:$dst)]>;
+ [(store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))),
+ addr:$dst)]>;
}
let Predicates = [HasAVX, NoBWI] in
@@ -5554,8 +5554,8 @@ multiclass SS41I_extract16<bits<8> opc,
(ins i16mem:$dst, VR128:$src1, u8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
- imm:$src2)))), addr:$dst)]>;
+ [(store (i16 (trunc (X86pextrw (v8i16 VR128:$src1), imm:$src2))),
+ addr:$dst)]>;
}
let Predicates = [HasAVX, NoBWI] in
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