[llvm] r316324 - [X86][F16C] Regenerate F16C schedule tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 07:15:24 PDT 2017
Author: rksimon
Date: Mon Oct 23 07:15:24 2017
New Revision: 316324
URL: http://llvm.org/viewvc/llvm-project?rev=316324&view=rev
Log:
[X86][F16C] Regenerate F16C schedule tests
Modified:
llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
Modified: llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=316324&r1=316323&r2=316324&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/f16c-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/f16c-schedule.ll Mon Oct 23 07:15:24 2017
@@ -13,49 +13,49 @@ define <4 x float> @test_vcvtph2ps_128(<
; GENERIC-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [7:1.00]
; GENERIC-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; GENERIC-NEXT: retq # sched: [1:1.00]
+; GENERIC-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; IVY-LABEL: test_vcvtph2ps_128:
; IVY: # BB#0:
; IVY-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [7:1.00]
; IVY-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
; IVY-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
+; IVY-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; HASWELL-LABEL: test_vcvtph2ps_128:
; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [1:1.00]
; HASWELL-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [2:1.00]
; HASWELL-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; HASWELL-NEXT: retq # sched: [2:1.00]
+; HASWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; BROADWELL-LABEL: test_vcvtph2ps_128:
; BROADWELL: # BB#0:
; BROADWELL-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [1:1.00]
; BROADWELL-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [2:1.00]
; BROADWELL-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; BROADWELL-NEXT: retq # sched: [2:1.00]
+; BROADWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; SKYLAKE-LABEL: test_vcvtph2ps_128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [9:0.50]
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [7:1.00]
+; SKYLAKE-NEXT: ret{{[l|q]}} # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtph2ps_128:
; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
+; BTVER2-NEXT: ret{{[l|q]}} # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtph2ps_128:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [100:?]
; ZNVER1-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; ZNVER1-NEXT: retq # sched: [1:0.50]
+; ZNVER1-NEXT: ret{{[l|q]}} # sched: [1:0.50]
%1 = load <8 x i16>, <8 x i16> *%a1
%2 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1)
%3 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0)
@@ -70,49 +70,49 @@ define <8 x float> @test_vcvtph2ps_256(<
; GENERIC-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [7:1.00]
; GENERIC-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
; GENERIC-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; GENERIC-NEXT: retq # sched: [1:1.00]
+; GENERIC-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; IVY-LABEL: test_vcvtph2ps_256:
; IVY: # BB#0:
; IVY-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [7:1.00]
; IVY-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
; IVY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
+; IVY-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; HASWELL-LABEL: test_vcvtph2ps_256:
; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [1:1.00]
; HASWELL-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [2:1.00]
; HASWELL-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; HASWELL-NEXT: retq # sched: [2:1.00]
+; HASWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; BROADWELL-LABEL: test_vcvtph2ps_256:
; BROADWELL: # BB#0:
; BROADWELL-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [1:1.00]
; BROADWELL-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [2:1.00]
; BROADWELL-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; BROADWELL-NEXT: retq # sched: [2:1.00]
+; BROADWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; SKYLAKE-LABEL: test_vcvtph2ps_256:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [7:1.00]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [7:1.00]
+; SKYLAKE-NEXT: ret{{[l|q]}} # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtph2ps_256:
; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
+; BTVER2-NEXT: ret{{[l|q]}} # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtph2ps_256:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [100:?]
; ZNVER1-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [100:?]
; ZNVER1-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; ZNVER1-NEXT: retq # sched: [1:0.50]
+; ZNVER1-NEXT: ret{{[l|q]}} # sched: [1:0.50]
%1 = load <8 x i16>, <8 x i16> *%a1
%2 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %1)
%3 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0)
@@ -126,43 +126,43 @@ define <8 x i16> @test_vcvtps2ph_128(<4
; GENERIC: # BB#0:
; GENERIC-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [7:1.00]
-; GENERIC-NEXT: retq # sched: [1:1.00]
+; GENERIC-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; IVY-LABEL: test_vcvtps2ph_128:
; IVY: # BB#0:
; IVY-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
; IVY-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [7:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
+; IVY-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; HASWELL-LABEL: test_vcvtps2ph_128:
; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [4:1.00]
-; HASWELL-NEXT: retq # sched: [2:1.00]
+; HASWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; BROADWELL-LABEL: test_vcvtps2ph_128:
; BROADWELL: # BB#0:
; BROADWELL-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [4:1.00]
; BROADWELL-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [4:1.00]
-; BROADWELL-NEXT: retq # sched: [2:1.00]
+; BROADWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; SKYLAKE-LABEL: test_vcvtps2ph_128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [6:1.00]
-; SKYLAKE-NEXT: retq # sched: [7:1.00]
+; SKYLAKE-NEXT: ret{{[l|q]}} # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtps2ph_128:
; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [8:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
+; BTVER2-NEXT: ret{{[l|q]}} # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtps2ph_128:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [100:?]
-; ZNVER1-NEXT: retq # sched: [1:0.50]
+; ZNVER1-NEXT: ret{{[l|q]}} # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
%2 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a1, i32 0)
%3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -177,48 +177,48 @@ define <8 x i16> @test_vcvtps2ph_256(<8
; GENERIC-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]
; GENERIC-NEXT: vzeroupper
-; GENERIC-NEXT: retq # sched: [1:1.00]
+; GENERIC-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; IVY-LABEL: test_vcvtps2ph_256:
; IVY: # BB#0:
; IVY-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
; IVY-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]
; IVY-NEXT: vzeroupper
-; IVY-NEXT: retq # sched: [1:1.00]
+; IVY-NEXT: ret{{[l|q]}} # sched: [1:1.00]
;
; HASWELL-LABEL: test_vcvtps2ph_256:
; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:1.00]
; HASWELL-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [6:1.00]
; HASWELL-NEXT: vzeroupper # sched: [4:1.00]
-; HASWELL-NEXT: retq # sched: [2:1.00]
+; HASWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; BROADWELL-LABEL: test_vcvtps2ph_256:
; BROADWELL: # BB#0:
; BROADWELL-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:1.00]
; BROADWELL-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [6:1.00]
; BROADWELL-NEXT: vzeroupper # sched: [4:1.00]
-; BROADWELL-NEXT: retq # sched: [2:1.00]
+; BROADWELL-NEXT: ret{{[l|q]}} # sched: [2:1.00]
;
; SKYLAKE-LABEL: test_vcvtps2ph_256:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [7:1.00]
+; SKYLAKE-NEXT: ret{{[l|q]}} # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtps2ph_256:
; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
+; BTVER2-NEXT: ret{{[l|q]}} # sched: [4:1.00]
;
; ZNVER1-LABEL: test_vcvtps2ph_256:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [100:?]
; ZNVER1-NEXT: vzeroupper # sched: [100:?]
-; ZNVER1-NEXT: retq # sched: [1:0.50]
+; ZNVER1-NEXT: ret{{[l|q]}} # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
%2 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a1, i32 0)
store <8 x i16> %2, <8 x i16> *%a2
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