[PATCH] D38676: [LV] Model masking in VPlan, introducing VPInstructions

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D38676#902541, @hsaito wrote:

> The design choice I'm advocating is that we should be able to make all of the vectorizer up to cost modeling can be made as a valid Analysis Pass.
>  That means no IR Instructions left unattached (if we do that, verifiers will complain). As a result, if we are to use IR instructions instead of VPInstructions
>  in VPlan, we have to either clone the entire Function, or create a new Function and copy the loop (nest) of interest to it. I hugely disagree to such a hack
>
> - hence have a desire to move forward with the VPInstruction direction.


Fully agreed! Thanks for the clarification.

--renato


https://reviews.llvm.org/D38676