[llvm] r316085 - [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
Andre Vieira via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 07:47:37 PDT 2017
Author: avieira
Date: Wed Oct 18 07:47:37 2017
New Revision: 316085
URL: http://llvm.org/viewvc/llvm-project?rev=316085&view=rev
Log:
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
Differential Revision: https://reviews.llvm.org/D38347
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt
llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=316085&r1=316084&r2=316085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Oct 18 07:47:37 2017
@@ -5340,8 +5340,14 @@ static DecodeStatus DecodeForVMRSandVMSR
} else
Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
- Inst.addOperand(MCOperand::createImm(ARMCC::AL));
- Inst.addOperand(MCOperand::createReg(0));
+ if (featureBits[ARM::ModeThumb]) {
+ Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+ Inst.addOperand(MCOperand::createReg(0));
+ } else {
+ unsigned pred = fieldFromInstruction(Val, 28, 4);
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
return S;
}
Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt?rev=316085&r1=316084&r2=316085&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt Wed Oct 18 07:47:37 2017
@@ -58,3 +58,54 @@
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
+
+ [0x10,0xfa,0xf1,0x0e]
+ [0x10,0xfa,0xf1,0x1e]
+ [0x10,0xfa,0xf1,0x2e]
+ [0x10,0xaa,0xf1,0x3e]
+ [0x10,0x2a,0xf0,0x4e]
+ [0x10,0x3a,0xf0,0x5e]
+ [0x10,0x4a,0xf7,0x6e]
+ [0x10,0x5a,0xf6,0x7e]
+ [0x10,0x6a,0xf5,0x8e]
+ [0x10,0xda,0xf1,0x9e]
+
+# CHECK-V7A: vmrseq APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x0e]
+# CHECK-V7A: vmrsne APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x1e]
+# CHECK-V7A: vmrshs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x2e]
+# CHECK-V7A: vmrslo r10, fpscr @ encoding: [0x10,0xaa,0xf1,0x3e]
+# CHECK-V7A: vmrsmi r2, fpsid @ encoding: [0x10,0x2a,0xf0,0x4e]
+# CHECK-V7A: vmrspl r3, fpsid @ encoding: [0x10,0x3a,0xf0,0x5e]
+# CHECK-V7A: vmrsvs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0x6e]
+# CHECK-V7A: vmrsvc r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0x7e]
+# ERROR-V7A: invalid instruction encoding
+# CHECK-V7A: vmrsls sp, fpscr @ encoding: [0x10,0xda,0xf1,0x9e]
+
+# CHECK-V8A: vmrseq APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x0e]
+# CHECK-V8A: vmrsne APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x1e]
+# CHECK-V8A: vmrshs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x2e]
+# CHECK-V8A: vmrslo r10, fpscr @ encoding: [0x10,0xaa,0xf1,0x3e]
+# CHECK-V8A: vmrsmi r2, fpsid @ encoding: [0x10,0x2a,0xf0,0x4e]
+# CHECK-V8A: vmrspl r3, fpsid @ encoding: [0x10,0x3a,0xf0,0x5e]
+# CHECK-V8A: vmrsvs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0x6e]
+# CHECK-V8A: vmrsvc r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0x7e]
+# CHECK-V8A: vmrshi r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0x8e]
+# CHECK-V8A: vmrsls sp, fpscr @ encoding: [0x10,0xda,0xf1,0x9e]
+
+ [0x10,0x0a,0xe1,0xae]
+ [0x10,0x1a,0xe8,0xbe]
+ [0x10,0x2a,0xe0,0xce]
+ [0x10,0xaa,0xe1,0xde]
+ [0x10,0xda,0xe1,0x0e]
+
+# CHECK-V7A: vmsrge fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xae]
+# CHECK-V7A: vmsrlt fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xbe]
+# CHECK-V7A: vmsrgt fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xce]
+# CHECK-V7A: vmsrle fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xde]
+# CHECK-V7A: vmsreq fpscr, sp @ encoding: [0x10,0xda,0xe1,0x0e]
+
+# CHECK-V8A: vmsrge fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xae]
+# CHECK-V8A: vmsrlt fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xbe]
+# CHECK-V8A: vmsrgt fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xce]
+# CHECK-V8A: vmsrle fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xde]
+# CHECK-V8A: vmsreq fpscr, sp @ encoding: [0x10,0xda,0xe1,0x0e]
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt?rev=316085&r1=316084&r2=316085&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt Wed Oct 18 07:47:37 2017
@@ -121,3 +121,37 @@
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
+ [0x0b,0xbf]
+ [0xf7,0xee,0x10,0x4a]
+ [0xf6,0xee,0x10,0x5a]
+ [0xe1,0xee,0x10,0x0a]
+ [0xe0,0xee,0x10,0x2a]
+
+# CHECK-V7A: itete eq @ encoding: [0x0b,0xbf]
+# CHECK-V7A: vmrseq r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
+# CHECK-V7A: vmrsne r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
+# CHECK-V7A: vmsreq fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+# CHECK-V7A: vmsrne fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
+
+# CHECK-V7M: itete eq @ encoding: [0x0b,0xbf]
+# CHECK-V7M: vmrseq r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
+# CHECK-V7M: vmrsne r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
+# CHECK-V7M: vmsreq fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+# CHECK-V7M: vmsrne fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
+
+# CHECK-V8A: itete eq @ encoding: [0x0b,0xbf]
+# CHECK-V8A: vmrseq r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
+# CHECK-V8A: vmrsne r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
+# CHECK-V8A: vmsreq fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+# CHECK-V8A: vmsrne fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
+
+# CHECK-V8M: itete eq @ encoding: [0x0b,0xbf]
+# CHECK-V8M: vmrseq r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
+# CHECK-V8M: vmrsne r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
+# CHECK-V8M: vmsreq fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+# CHECK-V8M: vmsrne fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
+
+# ERROR-NOVFP: invalid instruction encoding
+# ERROR-NOVFP: invalid instruction encoding
+# ERROR-NOVFP: invalid instruction encoding
+# ERROR-NOVFP: invalid instruction encoding
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