[PATCH] D38084: [ARM] add, or, shl combining

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:10101
 
+static SDValue PerformUnfoldSHL(SDNode *N,
+                                TargetLowering::DAGCombinerInfo &DCI,
----------------
'Unfold' is probably the wrong description of this as we may get these kind of instruction sequences without any folding having happened e.g.

```
int fn(int a, int b)
{
  return b + ((a << 1) | 510);
}
```


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:10104-10105
+                                const ARMSubtarget *ST) {
+  if (ST->isThumb() && ST->isThumb1Only())
+    return SDValue();
+
----------------
Could do with a comment here saying something like "no 16-bit thumb instructions with shifted operand".


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:10107-10108
+
+  if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR)
+    return SDValue();
+
----------------
We should be doing this for XOR and AND as well.


https://reviews.llvm.org/D38084