[PATCH] D39026: [NVPTX] allow address space inference for volatile loads/stores.

[Artem Belevich via Phabricator via llvm-commits]

tra created this revision.
Herald added subscribers: hiraditya, sanjoy, jholewinski.

If particular target supports volatile memory access operations, we can
avoid casting to generic AS. Currently it's only enabled in NVPTX for
loads and stores that access global & shared AS.

This improves performance in situations when we need to exchange data via shared memory 
and need to preserve memory access order using 'volatile'.


https://reviews.llvm.org/D39026

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
  llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
  llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py

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