[llvm] r315769 - Revert r315763: "[Hexagon] Rangify some loops, NFC"
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 13 14:57:11 PDT 2017
Author: kparzysz
Date: Fri Oct 13 14:57:11 2017
New Revision: 315769
URL: http://llvm.org/viewvc/llvm-project?rev=315769&view=rev
Log:
Revert r315763: "[Hexagon] Rangify some loops, NFC"
Broke some builds (using libstdc++).
Modified:
llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
Modified: llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/BitTracker.cpp?rev=315769&r1=315768&r2=315769&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/BitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/BitTracker.cpp Fri Oct 13 14:57:11 2017
@@ -181,8 +181,8 @@ namespace llvm {
} // end namespace llvm
void BitTracker::print_cells(raw_ostream &OS) const {
- for (const std::pair<unsigned, RegisterCell> P : Map)
- dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
+ for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I)
+ dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n";
}
BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F)
@@ -830,16 +830,18 @@ void BT::visitNonBranch(const MachineIns
<< " cell: " << ME.getCell(RU, Map) << "\n";
}
dbgs() << "Outputs:\n";
- for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
- RegisterRef RD(P.first);
- dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: "
+ for (CellMapType::iterator I = ResMap.begin(), E = ResMap.end();
+ I != E; ++I) {
+ RegisterRef RD(I->first);
+ dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: "
<< ME.getCell(RD, ResMap) << "\n";
}
}
// Iterate over all definitions of the instruction, and update the
// cells accordingly.
- for (const MachineOperand &MO : MI.operands()) {
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
// Visit register defs only.
if (!MO.isReg() || !MO.isDef())
continue;
@@ -924,11 +926,14 @@ void BT::visitBranchesFrom(const Machine
++It;
} while (FallsThrough && It != End);
+ using succ_iterator = MachineBasicBlock::const_succ_iterator;
+
if (!DefaultToAll) {
// Need to add all CFG successors that lead to EH landing pads.
// There won't be explicit branches to these blocks, but they must
// be processed.
- for (const MachineBasicBlock *SB : B.successors()) {
+ for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I) {
+ const MachineBasicBlock *SB = *I;
if (SB->isEHPad())
Targets.insert(SB);
}
@@ -939,27 +944,33 @@ void BT::visitBranchesFrom(const Machine
Targets.insert(&*Next);
}
} else {
- for (const MachineBasicBlock *SB : B.successors())
- Targets.insert(SB);
+ for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I)
+ Targets.insert(*I);
}
- for (const MachineBasicBlock *TB : Targets)
- FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
+ for (unsigned i = 0, n = Targets.size(); i < n; ++i) {
+ int TargetN = Targets[i]->getNumber();
+ FlowQ.push(CFGEdge(ThisN, TargetN));
+ }
}
void BT::visitUsesOf(unsigned Reg) {
if (Trace)
dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
- for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) {
- if (!InstrExec.count(&UseI))
+ using use_iterator = MachineRegisterInfo::use_nodbg_iterator;
+
+ use_iterator End = MRI.use_nodbg_end();
+ for (use_iterator I = MRI.use_nodbg_begin(Reg); I != End; ++I) {
+ MachineInstr *UseI = I->getParent();
+ if (!InstrExec.count(UseI))
continue;
- if (UseI.isPHI())
- visitPHI(UseI);
- else if (!UseI.isBranch())
- visitNonBranch(UseI);
+ if (UseI->isPHI())
+ visitPHI(*UseI);
+ else if (!UseI->isBranch())
+ visitNonBranch(*UseI);
else
- visitBranchesFrom(UseI);
+ visitBranchesFrom(*UseI);
}
}
@@ -982,8 +993,8 @@ void BT::subst(RegisterRef OldRR, Regist
(void)NME;
assert((OME-OMB == NME-NMB) &&
"Substituting registers of different lengths");
- for (std::pair<unsigned, RegisterCell&> P : Map) {
- RegisterCell &RC = P.second;
+ for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) {
+ RegisterCell &RC = I->second;
for (uint16_t i = 0, w = RC.width(); i < w; ++i) {
BitValue &V = RC[i];
if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg)
@@ -1034,9 +1045,10 @@ void BT::run() {
const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
unsigned MaxBN = 0;
- for (const MachineBasicBlock &B : MF) {
- assert(B.getNumber() >= 0 && "Disconnected block");
- unsigned BN = B.getNumber();
+ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+ I != E; ++I) {
+ assert(I->getNumber() >= 0 && "Disconnected block");
+ unsigned BN = I->getNumber();
if (BN > MaxBN)
MaxBN = BN;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=315769&r1=315768&r2=315769&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Fri Oct 13 14:57:11 2017
@@ -60,8 +60,12 @@ HexagonEvaluator::HexagonEvaluator(const
// der the initial sequence of formal parameters that are known to be
// passed via registers.
unsigned InVirtReg, InPhysReg = 0;
+ const Function &F = *MF.getFunction();
- for (const Argument &Arg : MF.getFunction()->args()) {
+ using arg_iterator = Function::const_arg_iterator;
+
+ for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
+ const Argument &Arg = *I;
Type *ATy = Arg.getType();
unsigned Width = 0;
if (ATy->isIntegerTy())
@@ -186,7 +190,8 @@ bool HexagonEvaluator::evaluate(const Ma
unsigned NumDefs = 0;
// Sanity verification: there should not be any defs with subregisters.
- for (const MachineOperand &MO : MI.operands()) {
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef())
continue;
NumDefs++;
@@ -235,7 +240,8 @@ bool HexagonEvaluator::evaluate(const Ma
// checking what kind of operand a given instruction has individually
// for each instruction, do it here. Global symbols as operands gene-
// rally do not provide any useful information.
- for (const MachineOperand &MO : MI.operands()) {
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
MO.isCPI())
return false;
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