[llvm] r315759 - [RegisterBankInfo] Cache the getMinimalPhysRegClass information
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 13 14:16:15 PDT 2017
Author: qcolombet
Date: Fri Oct 13 14:16:15 2017
New Revision: 315759
URL: http://llvm.org/viewvc/llvm-project?rev=315759&view=rev
Log:
[RegisterBankInfo] Cache the getMinimalPhysRegClass information
TargetRegisterInfo::getMinimalPhysRegClass is actually pretty expensive
because it has to iterate over all the register classes.
Cache this information as we need and get it so that we limit its usage.
Right now, we heavily rely on it, because this is how we get the mapping
for vregs defined by copies from physreg (i.e., the one that are ABI
related).
Improve compile time by up to 10% for that pass.
NFC
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=315759&r1=315758&r2=315759&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Fri Oct 13 14:16:15 2017
@@ -407,6 +407,10 @@ protected:
mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
MapOfInstructionMappings;
+ /// Getting the minimal register class of a physreg is expensive.
+ /// Cache this information as we get it.
+ mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
+
/// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
/// RegisterBank instances.
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
@@ -427,6 +431,11 @@ protected:
return *RegBanks[ID];
}
+ /// Get the MinimalPhysRegClass for Reg.
+ /// \pre Reg is a physical register.
+ const TargetRegisterClass &
+ getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const;
+
/// Try to get the mapping of \p MI.
/// See getInstrMapping for more details on what a mapping represents.
///
@@ -699,8 +708,8 @@ public:
/// virtual register.
///
/// \pre \p Reg != 0 (NoRegister).
- static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
- const TargetRegisterInfo &TRI);
+ unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const;
/// Check that information hold by this instance make sense for the
/// given \p TRI.
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp?rev=315759&r1=315758&r2=315759&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp Fri Oct 13 14:16:15 2017
@@ -221,9 +221,8 @@ uint64_t RegBankSelect::getRepairCost(
// into a new virtual register.
// We would also need to propagate this information in the
// repairing placement.
- unsigned Cost =
- RBI->copyCost(*DesiredRegBrank, *CurRegBank,
- RegisterBankInfo::getSizeInBits(MO.getReg(), *MRI, *TRI));
+ unsigned Cost = RBI->copyCost(*DesiredRegBrank, *CurRegBank,
+ RBI->getSizeInBits(MO.getReg(), *MRI, *TRI));
// TODO: use a dedicated constant for ImpossibleCost.
if (Cost != std::numeric_limits<unsigned>::max())
return Cost;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=315759&r1=315758&r2=315759&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Fri Oct 13 14:16:15 2017
@@ -84,7 +84,7 @@ const RegisterBank *
RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
if (TargetRegisterInfo::isPhysicalRegister(Reg))
- return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg));
+ return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI));
assert(Reg && "NoRegister does not have a register bank");
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
@@ -95,6 +95,19 @@ RegisterBankInfo::getRegBank(unsigned Re
return nullptr;
}
+const TargetRegisterClass &
+RegisterBankInfo::getMinimalPhysRegClass(unsigned Reg,
+ const TargetRegisterInfo &TRI) const {
+ assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ "Reg must be a physreg");
+ const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
+ if (RegRCIt != PhysRegMinimalRCs.end())
+ return *RegRCIt->second;
+ const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
+ PhysRegMinimalRCs[Reg] = PhysRC;
+ return *PhysRC;
+}
+
const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI) const {
@@ -441,13 +454,13 @@ void RegisterBankInfo::applyDefaultMappi
unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
const MachineRegisterInfo &MRI,
- const TargetRegisterInfo &TRI) {
+ const TargetRegisterInfo &TRI) const {
const TargetRegisterClass *RC = nullptr;
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// The size is not directly available for physical registers.
// Instead, we need to access a register class that contains Reg and
// get the size of that register class.
- RC = TRI.getMinimalPhysRegClass(Reg);
+ RC = &getMinimalPhysRegClass(Reg, TRI);
} else {
LLT Ty = MRI.getType(Reg);
unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
@@ -546,7 +559,8 @@ bool RegisterBankInfo::InstructionMappin
assert(MI.getParent() && MI.getMF() &&
"MI must be connected to a MachineFunction");
const MachineFunction &MF = *MI.getMF();
- (void)MF;
+ const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
+ (void)RBI;
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
const MachineOperand &MO = MI.getOperand(Idx);
@@ -564,7 +578,7 @@ bool RegisterBankInfo::InstructionMappin
(void)MOMapping;
// Register size in bits.
// This size must match what the mapping expects.
- assert(MOMapping.verify(getSizeInBits(
+ assert(MOMapping.verify(RBI->getSizeInBits(
Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
"Value mapping is invalid");
}
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