[llvm] r315648 - [SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Oct 12 17:18:58 2017
New Revision: 315648

URL: http://llvm.org/viewvc/llvm-project?rev=315648&view=rev
Log:
[SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types.

I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=315648&r1=315647&r2=315648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Oct 12 17:18:58 2017
@@ -1027,7 +1027,7 @@ SDValue SelectionDAG::getZeroExtendInReg
   assert(!VT.isVector() &&
          "getZeroExtendInReg should use the vector element type instead of "
          "the vector type!");
-  if (Op.getValueType() == VT) return Op;
+  if (Op.getValueType().getScalarType() == VT) return Op;
   unsigned BitWidth = Op.getScalarValueSizeInBits();
   APInt Imm = APInt::getLowBitsSet(BitWidth,
                                    VT.getSizeInBits());