[llvm] r315390 - CodeGen: Minor cleanups to use MachineInstr::getMF. NFC
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 10 16:50:49 PDT 2017
Author: bogner
Date: Tue Oct 10 16:50:49 2017
New Revision: 315390
URL: http://llvm.org/viewvc/llvm-project?rev=315390&view=rev
Log:
CodeGen: Minor cleanups to use MachineInstr::getMF. NFC
Since r315388 we have a shorter way to say this, so we'll replace
MI->getParent()->getParent() with MI->getMF() in a few places.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/MachineOutliner.cpp
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
llvm/trunk/lib/CodeGen/TargetSchedule.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Tue Oct 10 16:50:49 2017
@@ -310,9 +310,8 @@ bool InstructionSelector::executeMatchTa
int64_t NewOpcode = MatchTable[CurrentIdx++];
assert((size_t)NewInsnID == OutMIs.size() &&
"Expected to store MIs in order");
- OutMIs.push_back(
- MachineInstrBuilder(*State.MIs[OldInsnID]->getParent()->getParent(),
- State.MIs[OldInsnID]));
+ OutMIs.push_back(MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
+ State.MIs[OldInsnID]));
OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
DEBUG(dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs[" << NewInsnID
<< "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Tue Oct 10 16:50:49 2017
@@ -93,8 +93,7 @@ public:
/// Some constructors for easy use.
MachineIRBuilder() = default;
MachineIRBuilder(MachineFunction &MF) { setMF(MF); }
- MachineIRBuilder(MachineInstr &MI)
- : MachineIRBuilder(*MI.getParent()->getParent()) {
+ MachineIRBuilder(MachineInstr &MI) : MachineIRBuilder(*MI.getMF()) {
setInstr(MI);
}
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Oct 10 16:50:49 2017
@@ -744,7 +744,7 @@ void AsmPrinter::EmitFunctionEntryLabel(
/// emitComments - Pretty-print comments for instructions.
static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
AsmPrinter *AP) {
- const MachineFunction *MF = MI.getParent()->getParent();
+ const MachineFunction *MF = MI.getMF();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
// Check for spills and reloads
@@ -2846,7 +2846,7 @@ void AsmPrinter::emitXRayTable() {
void AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI,
SledKind Kind, uint8_t Version) {
- auto Fn = MI.getParent()->getParent()->getFunction();
+ auto Fn = MI.getMF()->getFunction();
auto Attr = Fn->getFnAttribute("function-instrument");
bool LogArgs = Fn->hasFnAttribute("xray-log-args");
bool AlwaysInstrument =
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Oct 10 16:50:49 2017
@@ -1148,7 +1148,7 @@ void DwarfDebug::beginInstruction(const
DebugHandlerBase::beginInstruction(MI);
assert(CurMI);
- const auto *SP = MI->getParent()->getParent()->getFunction()->getSubprogram();
+ const auto *SP = MI->getMF()->getFunction()->getSubprogram();
if (!SP || SP->getUnit()->getEmissionKind() == DICompileUnit::NoDebug)
return;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue Oct 10 16:50:49 2017
@@ -151,7 +151,7 @@ RegisterBankInfo::getInstrMappingImpl(co
// is important. The rest is not constrained.
unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
- const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineFunction &MF = *MI.getMF();
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
const MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -543,9 +543,9 @@ bool RegisterBankInfo::InstructionMappin
// For PHI, we only care about mapping the definition.
assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
"NumOperands must match, see constructor");
- assert(MI.getParent() && MI.getParent()->getParent() &&
+ assert(MI.getParent() && MI.getMF() &&
"MI must be connected to a MachineFunction");
- const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineFunction &MF = *MI.getMF();
(void)MF;
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
@@ -725,8 +725,8 @@ void RegisterBankInfo::OperandsMapper::p
// If we have a function, we can pretty print the name of the registers.
// Otherwise we will print the raw numbers.
const TargetRegisterInfo *TRI =
- getMI().getParent() && getMI().getParent()->getParent()
- ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo()
+ getMI().getParent() && getMI().getMF()
+ ? getMI().getMF()->getSubtarget().getRegisterInfo()
: nullptr;
bool IsFirst = true;
for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Oct 10 16:50:49 2017
@@ -1361,8 +1361,7 @@ static void InsertUncondBranch(MachineBa
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
/// values defined in MI which are also live/used by MI.
static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
- const TargetRegisterInfo *TRI = MI.getParent()->getParent()
- ->getSubtarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = MI.getMF()->getSubtarget().getRegisterInfo();
// Before stepping forward past MI, remember which regs were live
// before MI. This is needed to set the Undef flag only when reg is
@@ -1382,7 +1381,7 @@ static void UpdatePredRedefs(MachineInst
unsigned Reg = Clobber.first;
MachineOperand &Op = const_cast<MachineOperand&>(*Clobber.second);
MachineInstr *OpMI = Op.getParent();
- MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI);
+ MachineInstrBuilder MIB(*OpMI->getMF(), OpMI);
if (Op.isRegMask()) {
// First handle regmasks. They clobber any entries in the mask which
// means that we need a def for those registers.
Modified: llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugValues.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugValues.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugValues.cpp Tue Oct 10 16:50:49 2017
@@ -374,7 +374,7 @@ void LiveDebugValues::transferDebugValue
void LiveDebugValues::transferRegisterDef(MachineInstr &MI,
OpenRangesSet &OpenRanges,
const VarLocMap &VarLocIDs) {
- MachineFunction *MF = MI.getParent()->getParent();
+ MachineFunction *MF = MI.getMF();
const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
SparseBitVector<> KillSet;
@@ -450,7 +450,7 @@ void LiveDebugValues::transferSpillInst(
VarLocMap &VarLocIDs,
SpillMap &Spills) {
unsigned Reg;
- MachineFunction *MF = MI.getParent()->getParent();
+ MachineFunction *MF = MI.getMF();
if (!isSpillInstruction(MI, MF, Reg))
return;
Modified: llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp (original)
+++ llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Tue Oct 10 16:50:49 2017
@@ -401,7 +401,7 @@ bool LocalStackSlotPass::insertFrameRefe
continue;
}
- const MachineFunction *MF = MI.getParent()->getParent();
+ const MachineFunction *MF = MI.getMF();
const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Oct 10 16:50:49 2017
@@ -703,7 +703,7 @@ static LLT getTypeToPrint(const MachineI
}
void MIPrinter::print(const MachineInstr &MI) {
- const auto *MF = MI.getParent()->getParent();
+ const auto *MF = MI.getMF();
const auto &MRI = MF->getRegInfo();
const auto &SubTarget = MF->getSubtarget();
const auto *TRI = SubTarget.getRegisterInfo();
@@ -854,8 +854,7 @@ static const char *getTargetFlagName(con
void MIPrinter::printTargetFlags(const MachineOperand &Op) {
if (!Op.getTargetFlags())
return;
- const auto *TII =
- Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
+ const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
assert(TII && "expected instruction info");
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
OS << "target-flags(";
@@ -964,8 +963,8 @@ void MIPrinter::print(const MachineOpera
break;
case MachineOperand::MO_TargetIndex:
OS << "target-index(";
- if (const auto *Name = getTargetIndexName(
- *Op.getParent()->getParent()->getParent(), Op.getIndex()))
+ if (const auto *Name =
+ getTargetIndexName(*Op.getParent()->getMF(), Op.getIndex()))
OS << Name;
else
OS << "<unknown>";
@@ -1029,7 +1028,7 @@ void MIPrinter::print(const MachineOpera
OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
break;
case MachineOperand::MO_CFIIndex: {
- const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
+ const MachineFunction &MF = *Op.getParent()->getMF();
print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
break;
}
@@ -1038,7 +1037,7 @@ void MIPrinter::print(const MachineOpera
if (ID < Intrinsic::num_intrinsics)
OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
else {
- const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
+ const MachineFunction &MF = *Op.getParent()->getMF();
const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
OS << "intrinsic(@" << TII->getName(ID) << ')';
}
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Oct 10 16:50:49 2017
@@ -111,7 +111,7 @@ void ilist_traits<MachineInstr>::removeN
assert(N->getParent() && "machine instruction not in a basic block");
// Remove from the use/def lists.
- if (MachineFunction *MF = N->getParent()->getParent())
+ if (MachineFunction *MF = N->getMF())
N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
N->setParent(nullptr);
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Oct 10 16:50:49 2017
@@ -311,7 +311,7 @@ bool MachineOperand::isIdenticalTo(const
return true;
// Calculate the size of the RegMask
- const MachineFunction *MF = getParent()->getParent()->getParent();
+ const MachineFunction *MF = getParent()->getMF();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
@@ -1055,7 +1055,7 @@ MachineInstr::mergeMemRefsWith(const Mac
if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
return std::make_pair(nullptr, 0);
- MachineFunction *MF = getParent()->getParent();
+ MachineFunction *MF = getMF();
mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
MemBegin);
@@ -1307,8 +1307,8 @@ MachineInstr::getRegClassConstraint(unsi
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) const {
assert(getParent() && "Can't have an MBB reference here!");
- assert(getParent()->getParent() && "Can't have an MF reference here!");
- const MachineFunction &MF = *getParent()->getParent();
+ assert(getMF() && "Can't have an MF reference here!");
+ const MachineFunction &MF = *getMF();
// Most opcodes have fixed constraints in their MCInstrDesc.
if (!isInlineAsm())
@@ -1669,7 +1669,7 @@ bool MachineInstr::isSafeToMove(AliasAna
bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
bool UseTBAA) {
- const MachineFunction *MF = getParent()->getParent();
+ const MachineFunction *MF = getMF();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Oct 10 16:50:49 2017
@@ -917,8 +917,8 @@ bool MachineLICM::IsLoopInvariantInst(Ma
// However, if the physreg is known to always be caller saved/restored
// then this use is safe to hoist.
if (!MRI->isConstantPhysReg(Reg) &&
- !(TRI->isCallerPreservedPhysReg(Reg, *I.getParent()->getParent())))
- return false;
+ !(TRI->isCallerPreservedPhysReg(Reg, *I.getMF())))
+ return false;
// Otherwise it's safe to move.
continue;
} else if (!MO.isDead()) {
@@ -1191,7 +1191,7 @@ MachineInstr *MachineLICM::ExtractHoista
&LoadRegIndex);
if (NewOpc == 0) return nullptr;
const MCInstrDesc &MID = TII->get(NewOpc);
- MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFunction &MF = *MI->getMF();
const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
// Ok, we're unfolding. Create a temporary register and do the unfold.
unsigned Reg = MRI->createVirtualRegister(RC);
Modified: llvm/trunk/lib/CodeGen/MachineOutliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOutliner.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineOutliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineOutliner.cpp Tue Oct 10 16:50:49 2017
@@ -939,8 +939,7 @@ MachineOutliner::findCandidates(SuffixTr
// Emit a remark explaining why we didn't outline this candidate.
std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator> C =
RepeatedSequenceLocs[0];
- MachineOptimizationRemarkEmitter MORE(
- *(C.first->getParent()->getParent()), nullptr);
+ MachineOptimizationRemarkEmitter MORE(*(C.first->getMF()), nullptr);
MachineOptimizationRemarkMissed R(DEBUG_TYPE, "NotOutliningCheaper",
C.first->getDebugLoc(),
C.first->getParent());
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Tue Oct 10 16:50:49 2017
@@ -3353,7 +3353,7 @@ bool SwingSchedulerDAG::canUseLastOffset
unsigned BaseReg = MI->getOperand(BasePosLd).getReg();
// Look for the Phi instruction.
- MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+ MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
MachineInstr *Phi = MRI.getVRegDef(BaseReg);
if (!Phi || !Phi->isPHI())
return false;
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Oct 10 16:50:49 2017
@@ -2653,7 +2653,7 @@ void GenericScheduler::initialize(Schedu
void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {
- const MachineFunction &MF = *Begin->getParent()->getParent();
+ const MachineFunction &MF = *Begin->getMF();
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Avoid setting up the register pressure tracker for small regions to save
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Oct 10 16:50:49 2017
@@ -363,7 +363,7 @@ bool CoalescerPair::setRegisters(const M
Flipped = true;
}
- const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+ const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
// Eliminate DstSub on a physreg.
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Oct 10 16:50:49 2017
@@ -463,7 +463,7 @@ RegScavenger::spill(unsigned Reg, const
MachineBasicBlock::iterator &UseMI) {
// Find an available scavenging slot with size and alignment matching
// the requirements of the class RC.
- const MachineFunction &MF = *Before->getParent()->getParent();
+ const MachineFunction &MF = *Before->getMF();
const MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned NeedSize = TRI->getSpillSize(RC);
unsigned NeedAlign = TRI->getSpillAlignment(RC);
@@ -536,7 +536,7 @@ unsigned RegScavenger::scavengeRegister(
MachineBasicBlock::iterator I,
int SPAdj) {
MachineInstr &MI = *I;
- const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineFunction &MF = *MI.getMF();
// Consider all allocatable registers in the register class initially
BitVector Candidates = TRI->getAllocatableSet(MF, RC);
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp Tue Oct 10 16:50:49 2017
@@ -191,7 +191,7 @@ MachineInstr *TargetInstrInfo::commuteIn
MachineInstr *CommutedMI = nullptr;
if (NewMI) {
// Create a new instruction.
- MachineFunction &MF = *MI.getParent()->getParent();
+ MachineFunction &MF = *MI.getMF();
CommutedMI = MF.CloneMachineInstr(&MI);
} else {
CommutedMI = &MI;
@@ -438,7 +438,7 @@ static const TargetRegisterClass *canFol
assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
"Cannot fold physregs");
- const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+ const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
@@ -763,7 +763,7 @@ void TargetInstrInfo::reassociateOps(
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
- MachineFunction *MF = Root.getParent()->getParent();
+ MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
@@ -846,7 +846,7 @@ void TargetInstrInfo::genAlternativeCode
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
- MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
+ MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
// Select the previous instruction in the sequence based on the input pattern.
MachineInstr *Prev = nullptr;
@@ -870,7 +870,7 @@ void TargetInstrInfo::genAlternativeCode
bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
const MachineInstr &MI, AliasAnalysis *AA) const {
- const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Remat clients assume operand 0 is the defined register.
@@ -948,7 +948,7 @@ bool TargetInstrInfo::isReallyTriviallyR
}
int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
- const MachineFunction *MF = MI.getParent()->getParent();
+ const MachineFunction *MF = MI.getMF();
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
bool StackGrowsDown =
TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Tue Oct 10 16:50:49 2017
@@ -866,7 +866,7 @@ MachineBasicBlock *
TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
MachineBasicBlock *MBB) const {
MachineInstr *MI = &InitialMI;
- MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFunction &MF = *MI->getMF();
MachineFrameInfo &MFI = MF.getFrameInfo();
// We're handling multiple types of operands here:
Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=315390&r1=315389&r2=315390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Oct 10 16:50:49 2017
@@ -316,7 +316,7 @@ computeOutputLatency(const MachineInstr
// correctly append imp-use operands, and readsReg() strangely returns false
// for predicated defs.
unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
- const MachineFunction &MF = *DefMI->getParent()->getParent();
+ const MachineFunction &MF = *DefMI->getMF();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
return computeInstrLatency(DefMI);
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