[llvm] r315204 - [x86] regenerate test checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 9 08:01:58 PDT 2017
Author: spatel
Date: Mon Oct 9 08:01:58 2017
New Revision: 315204
URL: http://llvm.org/viewvc/llvm-project?rev=315204&view=rev
Log:
[x86] regenerate test checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/split-store.ll
Modified: llvm/trunk/test/CodeGen/X86/split-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-store.ll?rev=315204&r1=315203&r2=315204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/split-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/split-store.ll Mon Oct 9 08:01:58 2017
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -force-split-store < %s | FileCheck %s
-; CHECK-LABEL: int32_float_pair
-; CHECK-DAG: movl %edi, (%rsi)
-; CHECK-DAG: movss %xmm0, 4(%rsi)
define void @int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int32_float_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl %edi, (%rsi)
+; CHECK-NEXT: movss %xmm0, 4(%rsi)
+; CHECK-NEXT: retq
%t0 = bitcast float %tmp2 to i32
%t1 = zext i32 %t0 to i64
%t2 = shl nuw i64 %t1, 32
@@ -14,11 +16,12 @@ entry:
ret void
}
-; CHECK-LABEL: float_int32_pair
-; CHECK-DAG: movss %xmm0, (%rsi)
-; CHECK-DAG: movl %edi, 4(%rsi)
define void @float_int32_pair(float %tmp1, i32 %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: float_int32_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movss %xmm0, (%rsi)
+; CHECK-NEXT: movl %edi, 4(%rsi)
+; CHECK-NEXT: retq
%t0 = bitcast float %tmp1 to i32
%t1 = zext i32 %tmp2 to i64
%t2 = shl nuw i64 %t1, 32
@@ -28,12 +31,13 @@ entry:
ret void
}
-; CHECK-LABEL: int16_float_pair
-; CHECK-DAG: movzwl %di, %eax
-; CHECK-DAG: movl %eax, (%rsi)
-; CHECK-DAG: movss %xmm0, 4(%rsi)
define void @int16_float_pair(i16 signext %tmp1, float %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int16_float_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movzwl %di, %eax
+; CHECK-NEXT: movl %eax, (%rsi)
+; CHECK-NEXT: movss %xmm0, 4(%rsi)
+; CHECK-NEXT: retq
%t0 = bitcast float %tmp2 to i32
%t1 = zext i32 %t0 to i64
%t2 = shl nuw i64 %t1, 32
@@ -43,12 +47,13 @@ entry:
ret void
}
-; CHECK-LABEL: int8_float_pair
-; CHECK-DAG: movzbl %dil, %eax
-; CHECK-DAG: movl %eax, (%rsi)
-; CHECK-DAG: movss %xmm0, 4(%rsi)
define void @int8_float_pair(i8 signext %tmp1, float %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int8_float_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: movl %eax, (%rsi)
+; CHECK-NEXT: movss %xmm0, 4(%rsi)
+; CHECK-NEXT: retq
%t0 = bitcast float %tmp2 to i32
%t1 = zext i32 %t0 to i64
%t2 = shl nuw i64 %t1, 32
@@ -58,11 +63,12 @@ entry:
ret void
}
-; CHECK-LABEL: int32_int32_pair
-; CHECK: movl %edi, (%rdx)
-; CHECK: movl %esi, 4(%rdx)
define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int32_int32_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl %edi, (%rdx)
+; CHECK-NEXT: movl %esi, 4(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i32 %tmp2 to i64
%t2 = shl nuw i64 %t1, 32
%t3 = zext i32 %tmp1 to i64
@@ -71,11 +77,12 @@ entry:
ret void
}
-; CHECK-LABEL: int16_int16_pair
-; CHECK: movw %di, (%rdx)
-; CHECK: movw %si, 2(%rdx)
define void @int16_int16_pair(i16 signext %tmp1, i16 signext %tmp2, i32* %ref.tmp) {
-entry:
+; CHECK-LABEL: int16_int16_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movw %di, (%rdx)
+; CHECK-NEXT: movw %si, 2(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i16 %tmp2 to i32
%t2 = shl nuw i32 %t1, 16
%t3 = zext i16 %tmp1 to i32
@@ -84,11 +91,12 @@ entry:
ret void
}
-; CHECK-LABEL: int8_int8_pair
-; CHECK: movb %dil, (%rdx)
-; CHECK: movb %sil, 1(%rdx)
define void @int8_int8_pair(i8 signext %tmp1, i8 signext %tmp2, i16* %ref.tmp) {
-entry:
+; CHECK-LABEL: int8_int8_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movb %dil, (%rdx)
+; CHECK-NEXT: movb %sil, 1(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i8 %tmp2 to i16
%t2 = shl nuw i16 %t1, 8
%t3 = zext i8 %tmp1 to i16
@@ -97,13 +105,14 @@ entry:
ret void
}
-; CHECK-LABEL: int31_int31_pair
-; CHECK: andl $2147483647, %edi
-; CHECK: movl %edi, (%rdx)
-; CHECK: andl $2147483647, %esi
-; CHECK: movl %esi, 4(%rdx)
define void @int31_int31_pair(i31 %tmp1, i31 %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int31_int31_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
+; CHECK-NEXT: movl %edi, (%rdx)
+; CHECK-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
+; CHECK-NEXT: movl %esi, 4(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i31 %tmp2 to i64
%t2 = shl nuw i64 %t1, 32
%t3 = zext i31 %tmp1 to i64
@@ -112,13 +121,14 @@ entry:
ret void
}
-; CHECK-LABEL: int31_int17_pair
-; CHECK: andl $2147483647, %edi
-; CHECK: movl %edi, (%rdx)
-; CHECK: andl $131071, %esi
-; CHECK: movl %esi, 4(%rdx)
define void @int31_int17_pair(i31 %tmp1, i17 %tmp2, i64* %ref.tmp) {
-entry:
+; CHECK-LABEL: int31_int17_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
+; CHECK-NEXT: movl %edi, (%rdx)
+; CHECK-NEXT: andl $131071, %esi # imm = 0x1FFFF
+; CHECK-NEXT: movl %esi, 4(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i17 %tmp2 to i64
%t2 = shl nuw i64 %t1, 32
%t3 = zext i31 %tmp1 to i64
@@ -127,13 +137,14 @@ entry:
ret void
}
-; CHECK-LABEL: int7_int3_pair
-; CHECK: andb $127, %dil
-; CHECK: movb %dil, (%rdx)
-; CHECK: andb $7, %sil
-; CHECK: movb %sil, 1(%rdx)
define void @int7_int3_pair(i7 signext %tmp1, i3 signext %tmp2, i16* %ref.tmp) {
-entry:
+; CHECK-LABEL: int7_int3_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: andb $127, %dil
+; CHECK-NEXT: movb %dil, (%rdx)
+; CHECK-NEXT: andb $7, %sil
+; CHECK-NEXT: movb %sil, 1(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i3 %tmp2 to i16
%t2 = shl nuw i16 %t1, 8
%t3 = zext i7 %tmp1 to i16
@@ -142,15 +153,16 @@ entry:
ret void
}
-; CHECK-LABEL: int24_int24_pair
-; CHECK: movw %di, (%rdx)
-; CHECK: shrl $16, %edi
-; CHECK: movb %dil, 2(%rdx)
-; CHECK: movw %si, 4(%rdx)
-; CHECK: shrl $16, %esi
-; CHECK: movb %sil, 6(%rdx)
define void @int24_int24_pair(i24 signext %tmp1, i24 signext %tmp2, i48* %ref.tmp) {
-entry:
+; CHECK-LABEL: int24_int24_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movw %di, (%rdx)
+; CHECK-NEXT: shrl $16, %edi
+; CHECK-NEXT: movb %dil, 2(%rdx)
+; CHECK-NEXT: movw %si, 4(%rdx)
+; CHECK-NEXT: shrl $16, %esi
+; CHECK-NEXT: movb %sil, 6(%rdx)
+; CHECK-NEXT: retq
%t1 = zext i24 %tmp2 to i48
%t2 = shl nuw i48 %t1, 24
%t3 = zext i24 %tmp1 to i48
@@ -160,16 +172,18 @@ entry:
}
; getTypeSizeInBits(i12) != getTypeStoreSizeInBits(i12), so store split doesn't kick in.
-; CHECK-LABEL: int12_int12_pair
-; CHECK: movl %esi, %eax
-; CHECK: shll $12, %eax
-; CHECK: andl $4095, %edi
-; CHECK: orl %eax, %edi
-; CHECK: shrl $4, %esi
-; CHECK: movb %sil, 2(%rdx)
-; CHECK: movw %di, (%rdx)
+
define void @int12_int12_pair(i12 signext %tmp1, i12 signext %tmp2, i24* %ref.tmp) {
-entry:
+; CHECK-LABEL: int12_int12_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: shll $12, %eax
+; CHECK-NEXT: andl $4095, %edi # imm = 0xFFF
+; CHECK-NEXT: orl %eax, %edi
+; CHECK-NEXT: shrl $4, %esi
+; CHECK-NEXT: movb %sil, 2(%rdx)
+; CHECK-NEXT: movw %di, (%rdx)
+; CHECK-NEXT: retq
%t1 = zext i12 %tmp2 to i24
%t2 = shl nuw i24 %t1, 12
%t3 = zext i12 %tmp1 to i24
@@ -179,16 +193,18 @@ entry:
}
; getTypeSizeInBits(i14) != getTypeStoreSizeInBits(i14), so store split doesn't kick in.
-; CHECK-LABEL: int7_int7_pair
-; CHECK: movzbl %sil, %eax
-; CHECK: shll $7, %eax
-; CHECK: andb $127, %dil
-; CHECK: movzbl %dil, %ecx
-; CHECK: orl %eax, %ecx
-; CHECK: andl $16383, %ecx
-; CHECK: movw %cx, (%rdx)
+
define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, i14* %ref.tmp) {
-entry:
+; CHECK-LABEL: int7_int7_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl %sil, %eax
+; CHECK-NEXT: shll $7, %eax
+; CHECK-NEXT: andb $127, %dil
+; CHECK-NEXT: movzbl %dil, %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: andl $16383, %ecx # imm = 0x3FFF
+; CHECK-NEXT: movw %cx, (%rdx)
+; CHECK-NEXT: retq
%t1 = zext i7 %tmp2 to i14
%t2 = shl nuw i14 %t1, 7
%t3 = zext i7 %tmp1 to i14
@@ -198,14 +214,16 @@ entry:
}
; getTypeSizeInBits(i2) != getTypeStoreSizeInBits(i2), so store split doesn't kick in.
-; CHECK-LABEL: int1_int1_pair
-; CHECK: addb %sil, %sil
-; CHECK: andb $1, %dil
-; CHECK: orb %sil, %dil
-; CHECK: andb $3, %dil
-; CHECK: movb %dil, (%rdx)
+
define void @int1_int1_pair(i1 signext %tmp1, i1 signext %tmp2, i2* %ref.tmp) {
-entry:
+; CHECK-LABEL: int1_int1_pair:
+; CHECK: # BB#0:
+; CHECK-NEXT: addb %sil, %sil
+; CHECK-NEXT: andb $1, %dil
+; CHECK-NEXT: orb %sil, %dil
+; CHECK-NEXT: andb $3, %dil
+; CHECK-NEXT: movb %dil, (%rdx)
+; CHECK-NEXT: retq
%t1 = zext i1 %tmp2 to i2
%t2 = shl nuw i2 %t1, 1
%t3 = zext i1 %tmp1 to i2
@@ -214,10 +232,12 @@ entry:
ret void
}
-; CHECK-LABEL: mbb_int32_float_pair
-; CHECK: movl %edi, (%rsi)
-; CHECK: movss %xmm0, 4(%rsi)
define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) {
+; CHECK-LABEL: mbb_int32_float_pair:
+; CHECK: # BB#0: # %next
+; CHECK-NEXT: movl %edi, (%rsi)
+; CHECK-NEXT: movss %xmm0, 4(%rsi)
+; CHECK-NEXT: retq
entry:
%t0 = bitcast float %tmp2 to i32
br label %next
@@ -230,13 +250,18 @@ next:
ret void
}
-; CHECK-LABEL: mbb_int32_float_multi_stores
-; CHECK: movl %edi, (%rsi)
-; CHECK: movss %xmm0, 4(%rsi)
-; CHECK: # %bb2
-; CHECK: movl %edi, (%rdx)
-; CHECK: movss %xmm0, 4(%rdx)
define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, i64* %ref.tmp, i64* %ref.tmp1, i1 %cmp) {
+; CHECK-LABEL: mbb_int32_float_multi_stores:
+; CHECK: # BB#0: # %bb1
+; CHECK-NEXT: movl %edi, (%rsi)
+; CHECK-NEXT: movss %xmm0, 4(%rsi)
+; CHECK-NEXT: testb $1, %cl
+; CHECK-NEXT: je .LBB15_2
+; CHECK-NEXT: # BB#1: # %bb2
+; CHECK-NEXT: movl %edi, (%rdx)
+; CHECK-NEXT: movss %xmm0, 4(%rdx)
+; CHECK-NEXT: .LBB15_2: # %exitbb
+; CHECK-NEXT: retq
entry:
%t0 = bitcast float %tmp2 to i32
br label %bb1
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