[llvm] r315067 - [ARM] GlobalISel: Map shift operands to GPRs

[Diana Picus via llvm-commits]

Author: rovka
Date: Fri Oct  6 07:52:43 2017
New Revision: 315067

URL: http://llvm.org/viewvc/llvm-project?rev=315067&view=rev
Log:
[ARM] GlobalISel: Map shift operands to GPRs

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=315067&r1=315066&r2=315067&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Fri Oct  6 07:52:43 2017
@@ -218,6 +218,9 @@ ARMRegisterBankInfo::getInstrMapping(con
   case G_AND:
   case G_OR:
   case G_XOR:
+  case G_LSHR:
+  case G_ASHR:
+  case G_SHL:
   case G_SDIV:
   case G_UDIV:
   case G_SEXT:

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=315067&r1=315066&r2=315067&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Fri Oct  6 07:52:43 2017
@@ -20,6 +20,10 @@
   define void @test_or_s32() { ret void}
   define void @test_xor_s32() { ret void}
 
+  define void @test_lshr_s32() { ret void }
+  define void @test_ashr_s32() { ret void }
+  define void @test_shl_s32() { ret void }
+
   define void @test_loads() #0 { ret void }
   define void @test_stores() #0 { ret void }
 
@@ -505,6 +509,84 @@ body:             |
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
+...
+---
+name:            test_lshr_s32
+# CHECK-LABEL: name: test_lshr_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(s32) = G_LSHR %0, %1
+    %r0 = COPY %2(s32)
+    BX_RET 14, _, implicit %r0
+
+...
+---
+name:            test_ashr_s32
+# CHECK-LABEL: name: test_ashr_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(s32) = G_ASHR %0, %1
+    %r0 = COPY %2(s32)
+    BX_RET 14, _, implicit %r0
+
+...
+---
+name:            test_shl_s32
+# CHECK-LABEL: name: test_shl_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(s32) = G_SHL %0, %1
+    %r0 = COPY %2(s32)
+    BX_RET 14, _, implicit %r0
+
 ...
 ---
 name:            test_loads