[llvm] r314944 - AMDGPU: Fix not accounting for instruction size in bundles

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Oct  4 15:59:12 2017
New Revision: 314944

URL: http://llvm.org/viewvc/llvm-project?rev=314944&view=rev
Log:
AMDGPU: Fix not accounting for instruction size in bundles

These were counted as 0. Fixes branch limit exceeded errors
in some large programs.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/branch-relax-bundle.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=314944&r1=314943&r2=314944&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Oct  4 15:59:12 2017
@@ -4371,6 +4371,18 @@ unsigned SIInstrInfo::isStoreToStackSlot
   return AMDGPU::NoRegister;
 }
 
+unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {
+  unsigned Size = 0;
+  MachineBasicBlock::const_instr_iterator I = MI.getIterator();
+  MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
+  while (++I != E && I->isInsideBundle()) {
+    assert(!I->isBundle() && "No nested bundle!");
+    Size += getInstSizeInBytes(*I);
+  }
+
+  return Size;
+}
+
 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   unsigned Opc = MI.getOpcode();
   const MCInstrDesc &Desc = getMCOpcodeFromPseudo(Opc);
@@ -4414,9 +4426,10 @@ unsigned SIInstrInfo::getInstSizeInBytes
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
-  case TargetOpcode::BUNDLE:
   case TargetOpcode::EH_LABEL:
     return 0;
+  case TargetOpcode::BUNDLE:
+    return getInstBundleSize(MI);
   case TargetOpcode::INLINEASM: {
     const MachineFunction *MF = MI.getParent()->getParent();
     const char *AsmStr = MI.getOperand(0).getSymbolName();

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=314944&r1=314943&r2=314944&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Wed Oct  4 15:59:12 2017
@@ -818,6 +818,7 @@ public:
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
+  unsigned getInstBundleSize(const MachineInstr &MI) const;
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;

Added: llvm/trunk/test/CodeGen/AMDGPU/branch-relax-bundle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/branch-relax-bundle.ll?rev=314944&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/branch-relax-bundle.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/branch-relax-bundle.ll Wed Oct  4 15:59:12 2017
@@ -0,0 +1,53 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 < %s | FileCheck -check-prefix=GCN %s
+
+; Restrict maximum branch to between +15 and -16 dwords
+
+; Instructions inside a bundle were collectively counted as
+; 0-bytes. Make sure this is accounted for when estimating branch
+; distances
+
+; Bundle used for address in call sequence: 20 bytes
+; s_getpc_b64
+; s_add_u32
+; s_addc_u32
+
+; plus additional overhead
+; s_setpc_b64
+; and some register copies
+
+declare void @func() #0
+
+; GCN-LABEL: {{^}}bundle_size:
+; GCN: s_cbranch_scc0 [[BB_EXPANSION:BB[0-9]+_[0-9]+]]
+; GCN: s_getpc_b64
+; GCN-NEXT: s_add_u32
+; GCN-NEXT: s_addc_u32
+; GCN-NEXT: s_setpc_b64
+
+; GCN: {{^}}[[BB_EXPANSION]]:
+; GCN: s_getpc_b64
+; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@
+; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@
+; GCN: s_swappc_b64
+define amdgpu_kernel void @bundle_size(i32 addrspace(1)* %arg, i32 %cnd) #0 {
+bb:
+  %cmp = icmp eq i32 %cnd, 0
+  br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
+
+bb2:
+  call void @func()
+  call void asm sideeffect
+  "v_nop_e64
+   v_nop_e64
+   v_nop_e64
+   v_nop_e64
+   v_nop_e64", ""() #0
+  br label %bb3
+
+bb3:
+  store volatile i32 %cnd, i32 addrspace(1)* %arg
+  ret void
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }