[PATCH] D37348: Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Needs more comprehensive check lines. Just checking the instructions won't demonstrate that the extra instructions you're trying to avoid aren't there



================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3028
 
-  SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, DL, MVT::i32, Op);
+  SDValue FFBX = DAG.getNode(AMDGPUISDOpc, DL, MVT::i32, Op);
   if (VT != MVT::i32)
----------------
Don't include AMDGPUISD in the name of this


================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3053
 
+  unsigned AMDGPUISDOpc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
+                                           AMDGPUISD::FFBH_U32;
----------------
Ditto


================
Comment at: test/CodeGen/AMDGPU/cttz_zero_undef.ll:85
+; FUNC-LABEL: {{^}}s_cttz_zero_undef_i8_with_select:
+; SI: s_ff1_i32_b32
+; EG: MEM_RAT MSKOR 
----------------
This needs to check more


================
Comment at: test/CodeGen/AMDGPU/cttz_zero_undef.ll:97
+; FUNC-LABEL: {{^}}s_cttz_zero_undef_i16_with_select:
+; SI: s_ff1_i32_b32
+; EG: MEM_RAT MSKOR 
----------------
This needs to check more


================
Comment at: test/CodeGen/AMDGPU/cttz_zero_undef.ll:121-122
+; FUNC-LABEL: {{^}}s_cttz_zero_undef_i64_with_select:
+; SI: s_ff1_i32_b32
+; SI: s_ff1_i32_b32
+; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
----------------
Ditto


Repository:
  rL LLVM

https://reviews.llvm.org/D37348