[llvm] r314897 - [AVR] Factor out mayLoad in tablegen patterns

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Wed Oct  4 03:36:07 2017
New Revision: 314897

URL: http://llvm.org/viewvc/llvm-project?rev=314897&view=rev
Log:
[AVR] Factor out mayLoad in tablegen patterns

Patch by Gergo Erdi.

Modified:
    llvm/trunk/lib/Target/AVR/AVRInstrInfo.td

Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=314897&r1=314896&r2=314897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Wed Oct  4 03:36:07 2017
@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
 // Load program memory operations.
 let canFoldAsLoad = 1,
 isReMaterializable = 1,
+mayLoad = 1,
 hasSideEffects = 0 in
 {
   let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
                Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
-  let mayLoad = 1,
-  Defs = [R31R30] in
+  let Defs = [R31R30] in
   {
     def LPMRdZPi : FLPMX<0,
                          1,