[llvm] r314627 - [x86] formatting; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 1 07:39:10 PDT 2017
Author: spatel
Date: Sun Oct 1 07:39:10 2017
New Revision: 314627
URL: http://llvm.org/viewvc/llvm-project?rev=314627&view=rev
Log:
[x86] formatting; NFC
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=314627&r1=314626&r2=314627&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Oct 1 07:39:10 2017
@@ -16501,8 +16501,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
UI->getOpcode() != ISD::STORE)
goto default_case;
- if (ConstantSDNode *C =
- dyn_cast<ConstantSDNode>(ArithOp.getOperand(1))) {
+ if (auto *C = dyn_cast<ConstantSDNode>(ArithOp.getOperand(1))) {
// An add of one will be selected as an INC.
if (C->isOne() &&
(!Subtarget.slowIncDec() ||
@@ -16719,8 +16718,7 @@ SDValue X86TargetLowering::EmitCmp(SDVal
}
// Use SUB instead of CMP to enable CSE between SUB and CMP.
SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
- SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
- Op0, Op1);
+ SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1);
return SDValue(Sub.getNode(), 1);
}
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
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