[llvm] r314497 - [mips] Reordering callseq* nodes to be linear
Aleksandar Beserminji via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 29 02:32:14 PDT 2017
Author: abeserminji
Date: Fri Sep 29 02:32:14 2017
New Revision: 314497
URL: http://llvm.org/viewvc/llvm-project?rev=314497&view=rev
Log:
[mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.
Differential Revision: https://reviews.llvm.org/D37328
Added:
llvm/trunk/test/CodeGen/Mips/callseq_order.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Sep 29 02:32:14 2017
@@ -2992,16 +2992,6 @@ MipsTargetLowering::LowerCall(TargetLowe
if (IsTailCall)
++NumTailCalls;
- // Chain is the output chain of the last Load/Store or CopyToReg node.
- // ByValChain is the output chain of the last Memcpy node created for copying
- // byval arguments to the stack.
- unsigned StackAlignment = TFL->getStackAlignment();
- NextStackOffset = alignTo(NextStackOffset, StackAlignment);
- SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
-
- if (!IsTailCall)
- Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
-
SDValue StackPtr =
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
getPointerTy(DAG.getDataLayout()));
@@ -3030,7 +3020,7 @@ MipsTargetLowering::LowerCall(TargetLowe
assert(ByValIdx < CCInfo.getInRegsParamsCount());
assert(!IsTailCall &&
"Do not tail-call optimize if there is a byval argument.");
- passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
+ Chain = passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
VA);
CCInfo.nextInRegsParam();
@@ -3122,6 +3112,16 @@ MipsTargetLowering::LowerCall(TargetLowe
EVT Ty = Callee.getValueType();
bool GlobalOrExternal = false, IsCallReloc = false;
+ // Chain is the output chain of the last Load/Store or CopyToReg node.
+ // ByValChain is the output chain of the last Memcpy node created for copying
+ // byval arguments to the stack.
+ unsigned StackAlignment = TFL->getStackAlignment();
+ NextStackOffset = alignTo(NextStackOffset, StackAlignment);
+ SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
+
+ if (!IsTailCall)
+ Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
+
// The long-calls feature is ignored in case of PIC.
// While we do not support -mshared / -mno-shared properly,
// ignore long-calls in case of -mabicalls too.
@@ -4095,7 +4095,7 @@ void MipsTargetLowering::copyByValRegs(
}
// Copy byVal arg to registers and stack.
-void MipsTargetLowering::passByValArg(
+SDValue MipsTargetLowering::passByValArg(
SDValue Chain, const SDLoc &DL,
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
@@ -4128,7 +4128,7 @@ void MipsTargetLowering::passByValArg(
// Return if the struct has been fully copied.
if (ByValSizeInBytes == OffsetInBytes)
- return;
+ return Chain;
// Copy the remainder of the byval argument with sub-word loads and shifts.
if (LeftoverBytes) {
@@ -4173,7 +4173,7 @@ void MipsTargetLowering::passByValArg(
unsigned ArgReg = ArgRegs[FirstReg + I];
RegsToPass.push_back(std::make_pair(ArgReg, Val));
- return;
+ return Chain;
}
}
@@ -4183,12 +4183,13 @@ void MipsTargetLowering::passByValArg(
DAG.getConstant(OffsetInBytes, DL, PtrTy));
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
- Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
- DAG.getConstant(MemCpySize, DL, PtrTy),
- Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
- /*isTailCall=*/false,
- MachinePointerInfo(), MachinePointerInfo());
+ Chain = DAG.getMemcpy(
+ Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment,
+ /*isVolatile=*/false, /*AlwaysInline=*/false,
+ /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
MemOpChains.push_back(Chain);
+
+ return Chain;
}
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Fri Sep 29 02:32:14 2017
@@ -573,13 +573,13 @@ class TargetRegisterClass;
MipsCCState &State) const;
/// passByValArg - Pass a byval argument in registers or on stack.
- void passByValArg(SDValue Chain, const SDLoc &DL,
- std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
- SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
- MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
- unsigned FirstReg, unsigned LastReg,
- const ISD::ArgFlagsTy &Flags, bool isLittle,
- const CCValAssign &VA) const;
+ SDValue passByValArg(SDValue Chain, const SDLoc &DL,
+ std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
+ SmallVectorImpl<SDValue> &MemOpChains,
+ SDValue StackPtr, MachineFrameInfo &MFI,
+ SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
+ unsigned LastReg, const ISD::ArgFlagsTy &Flags,
+ bool isLittle, const CCValAssign &VA) const;
/// writeVarArgRegs - Write variable function arguments passed in registers
/// to the stack. Also create a stack frame object for the first variable
Added: llvm/trunk/test/CodeGen/Mips/callseq_order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/callseq_order.ll?rev=314497&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/callseq_order.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/callseq_order.ll Fri Sep 29 02:32:14 2017
@@ -0,0 +1,55 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips64el-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips64-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+
+
+%struct.Str1 = type { [64 x i32] }
+
+ at s1 = common global %struct.Str1 zeroinitializer, align 4
+
+define void @foo1() {
+entry:
+ call void @bar1(%struct.Str1* byval align 4 @s1)
+ ret void
+ ; CHECK-LABEL: *** MachineFunction at end of ISel ***
+ ; CHECK-LABEL: # Machine code for function foo1: IsSSA, TracksLiveness
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <ga:@bar1>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK-LABEL: # End machine code for function foo1.
+}
+
+declare void @bar1(%struct.Str1* byval align 4)
+
+define void @foo2() {
+entry:
+ call void @bar2(%struct.Str1* byval align 4 @s1, %struct.Str1* byval align 4 @s1)
+ ret void
+ ; CHECK-LABEL: *** MachineFunction at end of ISel ***
+ ; CHECK-LABEL: # Machine code for function foo2: IsSSA, TracksLiveness
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <ga:@bar2>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK-LABEL: # End machine code for function foo2.
+}
+
+declare void @bar2(%struct.Str1* byval align 4, %struct.Str1* byval align 4)
+
Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Sep 29 02:32:14 2017
@@ -1,8 +1,9 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefix=64
+; RUN: llc -march=mipsel -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN: FileCheck %s -check-prefix=32
+; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic \
+; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
%struct.S1 = type { [65536 x i8] }
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Fri Sep 29 02:32:14 2017
@@ -268,7 +268,7 @@ entry:
; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7
- ; MM32: lw $25, %call16(__multi3)($16)
+ ; MM32: lw $25, %call16(__multi3)
%r = mul i128 %a, %b
ret i128 %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll Fri Sep 29 02:32:14 2017
@@ -190,7 +190,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
; 64R6: ld $25, %call16(__divti3)($gp)
- ; MM32: lw $25, %call16(__divti3)($16)
+ ; MM32: lw $25, %call16(__divti3)
; MM64: ld $25, %call16(__divti3)($2)
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll Fri Sep 29 02:32:14 2017
@@ -182,7 +182,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
- ; MM32: lw $25, %call16(__modti3)($16)
+ ; MM32: lw $25, %call16(__modti3)
; MM64: ld $25, %call16(__modti3)($2)
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll Fri Sep 29 02:32:14 2017
@@ -152,7 +152,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
; 64-R6: ld $25, %call16(__udivti3)($gp)
- ; MM32: lw $25, %call16(__udivti3)($16)
+ ; MM32: lw $25, %call16(__udivti3)
; MM64: ld $25, %call16(__udivti3)($2)
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll?rev=314497&r1=314496&r2=314497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll Fri Sep 29 02:32:14 2017
@@ -208,7 +208,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
; 64R6: ld $25, %call16(__umodti3)($gp)
- ; MM32: lw $25, %call16(__umodti3)($16)
+ ; MM32: lw $25, %call16(__umodti3)
; MM64: ld $25, %call16(__umodti3)($2)
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