[PATCH] D38315: [ARM] Add f16 type support and code generation (part 1/2)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

This adds the groundwork for FP16 code generation:

- ARM_AAPCS_VFP is modified: the half-precision floats sit in the single-precision registers (the lower 16 bits), and in the other cases f16 values are promoted.
- A new register class HPR has been introduced to model this.
- To test code generation, match patterns for fsub and fadd have been added.

  In follow-up patch part 2/2, the remaining instructions will be added (this is just to keep the review manageable).


https://reviews.llvm.org/D38315

Files:
  lib/Target/ARM/ARMCallingConv.td
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMInstrVFP.td
  lib/Target/ARM/ARMRegisterInfo.td
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  test/CodeGen/ARM/fp16-instructions.ll

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