[PATCH] D38276: [X86] Remove dead code from X86ISelDAGToDAG.cpp multiply handling

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Rough outline of mul handling as I understand it.

-A plain mul i8 in IR will go through pretty much untouched and be pattern matched to MUL8r/MUL8m during isel.
-X86ISD::UMUL8/SMUL8 are created from i8 mul with overflow intrinsics. Requires special isel handling due to fixed register constraints on the MUL8r instruction which is made worse by the isel pattern for plain mul that caused the implicit defs list to be in a weird order.
-X86ISD::UMUL is created by i16/i32/i64 multiply with overflow intrinsics. Requires special isel handling due to fixed register constraints on the MUL16r/MUL32r/MUL64r instructions. I don't believe we ever use the high half result of this SDNode. Just the low data and the overflow flag. But there is no unsigned mul instruction that doesn't produce high data.
-X86ISD::SMUL is created by i16/i32/i64 multiply with overflow intrinsics. But we pattern match those to IMUL16rr/IMUL32rr/IMUL64rr. These instruction don't produce high data.
-A i32 umul_lohi/smul_lohi will be created for an i64 multiply on 32-bit targets. A i64 umul_lohi/smul_lohi will be created for i128 multiply on 64-bit targets.
-ISD::UMUL_LOHI/SMUL_LOHI can be produced directly by sdiv/udiv by constants for i8/i16/i32/i64. We're only using the high half so it briefly becomes ISDI::MULHU/MULHS pre-legalization, but is converted back to umul_lohi/smul_lohi during legalization.
-DAGCombiner turns ISD::UMUL_LOHI/SMUL_LOHI into regular multiplies and shifts when possible which should remove the ones created for divides.


https://reviews.llvm.org/D38276