[PATCH] D37514: [PowerPC] support ZERO_EXTEND in tryBitPermutation

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added a comment.

I apologize for taking so long to get back to this. The bit-permutation selector uses a cost model to decide how to lower each permutation sequence. Preemptively lowering the zext like this during the analysis phase of the algorithm seems suboptimal (or at least ad hoc).

In BitPermutationSelector, the ValueBit type can have one of two kinds: Variable or ConstZero. What we should do here to handle zext is, upon encountering the `ISD::ZERO_EXTEND` node, we should simply recurse by calling getValueBits(V.getOperand(0), <number of operand bits>). After recursing, we should take the gathered bits, extend the result with ValueBit(ValueBit::ConstZero) (similar to how ISD::AND is handled now).

I believe that the remainder of the algorithm will work as-is, except, that in the code that actually selects the machine instructions: the code called from Select64 -- and perhaps Select32 if we're extending from i1, although you might omit this by only handling i32 -> i64 zext), you'll need to check that the incoming values are all i64. If they're not, you'll then want to convert them to i64 using INSERT_SUBREG (as you're doing here). You could even do this as a pre-pass over all of the BitGroups to avoid complicating the rest of the code (by keeping a map to avoid inserting more insert_subregs than necessary: you want only one per incoming i32 value).


https://reviews.llvm.org/D37514