[PATCH] D38251: [X86] Remove erroneous callsite offsetting in SJLJ landing pads

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo updated this revision to Diff 116599.
mstorsjo added a comment.

Updated a missed comment in the test.


https://reviews.llvm.org/D38251

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/sjlj-eh.ll


Index: test/CodeGen/X86/sjlj-eh.ll
===================================================================
--- test/CodeGen/X86/sjlj-eh.ll
+++ test/CodeGen/X86/sjlj-eh.ll
@@ -60,13 +60,12 @@
 ;
 ; CHECK: [[RESUME]]:
 ; CHECK: leal -64(%ebp), %esi
-;     assert(UFC.__callsite <= 1);
+;     assert(UFC.__callsite < 1);
 ; CHECK: movl -60(%ebp), %eax
 ; CHECK: cmpl $1, %eax
-; CHECK: jbe [[CONT:LBB[0-9]+_[0-9]+]]
+; CHECK: jb [[CONT:LBB[0-9]+_[0-9]+]]
 ; CHECK: ud2
 ; CHECK: [[CONT]]:
-;     *Handlers[--UFC.__callsite]
-; CHECK: subl $1, %eax
+;     *Handlers[UFC.__callsite]
 ; CHECK: jmpl *LJTI
 
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -26574,17 +26574,13 @@
   BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
       .addReg(IReg)
       .addImm(LPadList.size());
-  BuildMI(DispatchBB, DL, TII->get(X86::JA_1)).addMBB(TrapBB);
+  BuildMI(DispatchBB, DL, TII->get(X86::JAE_1)).addMBB(TrapBB);
 
-  unsigned JReg = MRI->createVirtualRegister(&X86::GR32RegClass);
-  BuildMI(DispContBB, DL, TII->get(X86::SUB32ri), JReg)
-      .addReg(IReg)
-      .addImm(1);
   BuildMI(DispContBB, DL,
           TII->get(Subtarget.is64Bit() ? X86::JMP64m : X86::JMP32m))
       .addReg(0)
       .addImm(Subtarget.is64Bit() ? 8 : 4)
-      .addReg(JReg)
+      .addReg(IReg)
       .addJumpTableIndex(MJTI)
       .addReg(0);
 


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