[PATCH] D38254: [X86] Fix SJLJ struct offsets for x86_64

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo created this revision.

This is necessary, but not sufficient, to have working SJLJ exception handling on x86_64.


https://reviews.llvm.org/D38254

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/sjlj-eh.ll


Index: test/CodeGen/X86/sjlj-eh.ll
===================================================================
--- test/CodeGen/X86/sjlj-eh.ll
+++ test/CodeGen/X86/sjlj-eh.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple i386-windows-gnu -exception-model sjlj -filetype asm -o - %s | FileCheck %s
+; RUN: llc -mtriple x86_64-windows-gnu -exception-model sjlj -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-X64
 
 declare void @_Z20function_that_throwsv()
 declare i32 @__gxx_personality_sj0(...)
@@ -69,3 +70,50 @@
 ;     *Handlers[UFC.__callsite]
 ; CHECK: jmpl *LJTI
 
+
+;     struct _Unwind_FunctionContext {
+; +00   struct _Unwind_FunctionContext *prev;   -312(%rbp)
+; +08   uint32_t __callsite;                    -304(%rbp)
+; +12   uint32_t __buffer[4];                   -300(%rbp)
+; +32   __personality_routine __personality;    -280(%rbp)
+; +40   uintptr_t __lsda;                       -272(%rbp)
+; +48   void *__jbuf[];                         -264(%rbp)
+;     };
+
+
+; CHECK-X64-LABEL: _Z8functionv:
+;     struct _Unwind_FunctionContext UFC;
+;
+;     UFC.__personality = __gxx_personality_sj0
+; CHECK-X64: leaq __gxx_personality_sj0(%rip), %rax
+; CHECK-X64: movq %rax, -280(%rbp)
+;     UFC.__lsda = $LSDA
+; CHECK-X64: movl $[[LSDA:GCC_except_table[0-9]+]], %eax
+; CHECK-X64: movq %rax, -272(%rbp)
+;     UFC.__jbuf[0] = $RBP
+; CHECK-X64: movq %rbp, -264(%rbp)
+;     UFC.__jbuf[2] = $RSP
+; CHECK-X64: movq %rsp, -248(%rbp)
+;     UFC.__jbuf[1] = $RIP
+; CHECK-X64: leaq .[[RESUME:LBB[0-9]+_[0-9]+]](%rip), %rax
+; CHECK-X64: movq %rax, -256(%rbp)
+;     UFC.__callsite = 1
+; CHECK-X64: movl $1, -304(%rbp)
+;     _Unwind_SjLj_Register(&UFC);
+; CHECK-X64: leaq -312(%rbp), %rcx
+; CHECK-X64: callq _Unwind_SjLj_Register
+;     function_that_throws();
+; CHECK-X64: callq _Z20function_that_throwsv
+;     _Unwind_SjLj_Unregister(&UFC);
+; CHECK-X64: leaq -312(%rbp), %rcx
+; CHECK-X64: callq _Unwind_SjLj_Unregister
+;
+; CHECK-X64: [[RESUME]]:
+;     assert(UFC.__callsite <= 1);
+; CHECK-X64: movl -304(%rbp), %eax
+; CHECK-X64: cmpl $1, %eax
+; CHECK-X64: jb .[[CONT:LBB[0-9]+_[0-9]+]]
+; CHECK-X64: ud2
+; CHECK-X64: [[CONT]]:
+;     *Handlers[UFC.__callsite]
+; CHECK-X64: jmpq *.LJTI
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -26462,7 +26462,7 @@
   }
 
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(Op));
-  addFrameReference(MIB, FI, 36);
+  addFrameReference(MIB, FI, Subtarget.is64Bit() ? 56 : 36);
   if (UseImmLabel)
     MIB.addMBB(DispatchBB);
   else
@@ -26570,7 +26570,7 @@
 
   unsigned IReg = MRI->createVirtualRegister(&X86::GR32RegClass);
   addFrameReference(BuildMI(DispatchBB, DL, TII->get(X86::MOV32rm), IReg), FI,
-                    4);
+                    Subtarget.is64Bit() ? 8 : 4);
   BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
       .addReg(IReg)
       .addImm(LPadList.size());


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