[PATCH] D38053: [AArch64] Implement R_AARCH64_ LD_PREL_LO19

[Peter Smith via Phabricator via llvm-commits]

peter.smith added a comment.

Only thing I can spot is that I think that we are missing an alignment check on the result, otherwise looks good to me as well. The address of the value to be loaded must be at least 4-byte aligned. BFD has implemented this check, for example if I change the test case a little:

  ldr x8, patatino
  
          .data
          .zero 5
  patatino:

BFD will give me t.o:(.text+0x0): relocation truncated to fit: R_AARCH64_LD_PREL_LO19 against `.data', which is BFD's rather obtuse way of reporting alignment faults. The target of the conditional branch (R_AARCH64_CONDBR19) must be an instruction, which must be 4 byte aligned for AArch64, so I think it is safe to add a check for that as well. It is harder to write a realistic test case for that one though.

You can find the details of the instruction ldr (literal) in the architecture reference manual https://developer.arm.com/products/architecture/a-profile/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile


https://reviews.llvm.org/D38053