[PATCH] D35635: Optimize {s,u}{add,sub}.with.overflow on ARM

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

The change to getARMXALUOOp is wrong; ADDC produces two results, so you're making a node with the wrong type.

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So on trunk, for the llvm.uadd.with.overflow.i32 case, we produce a sequence like this:

  adds    r0, r0, r1
  mov     r2, #0
  adc     r1, r2, #0
  cmp     r1, #1

This is obviously not great... but the ARMISD::ADDE+ARMISD::CMP pattern is something you could DAGCombine away after legalization.  I would prefer to do that, rather than try to clean it up after isel.  Everything gets more complicated when you're dealing with MachineInstrs (you might end up optimizing simple cases, but not more complex ones), and the pattern works automatically with llvm.uadd.with.overflow.i64 etc.

I haven't thought through how exactly that extends to signed overflow, though.


https://reviews.llvm.org/D35635