[llvm] r313685 - [MIRPrinter] Print empty successor lists when they cannot be guessed

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Tue Sep 19 14:55:51 2017
New Revision: 313685

URL: http://llvm.org/viewvc/llvm-project?rev=313685&view=rev
Log:
[MIRPrinter] Print empty successor lists when they cannot be guessed

Unreachable blocks in the machine instr representation are these
weird empty blocks with no successors.
The MIR printer used to not print empty lists of successors. However,
the MIR parser now treats non-printed list of successors as "please
guess it for me". As a result, the parser tries to guess the list of
successors and given the block is empty, just assumes it falls through
the next block (if any).

For instance, the following test case used to fail the verifier.
The MIR printer would print
          entry
         /      \
    true (def)   false (no list of successors)
        |
  split.true (use)

The MIR parser would understand this:
          entry
         /      \
    true (def)   false
        |        /  <-- invalid edge
  split.true (use)

Because of the invalid edge, we get the "def does not
dominate all uses" error.

The fix consists in printing empty successor lists, so that the parser
knows what to do for unreachable blocks.

rdar://problem/34022159

Added:
    llvm/trunk/test/CodeGen/MIR/X86/unreachable_block.ll
Modified:
    llvm/trunk/lib/CodeGen/MIRPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=313685&r1=313684&r2=313685&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Sep 19 14:55:51 2017
@@ -598,8 +598,7 @@ void MIPrinter::print(const MachineBasic
   bool HasLineAttributes = false;
   // Print the successors
   bool canPredictProbs = canPredictBranchProbabilities(MBB);
-  if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs ||
-                            !canPredictSuccessors(MBB))) {
+  if (!SimplifyMIR || !canPredictProbs || !canPredictSuccessors(MBB)) {
     OS.indent(2) << "successors: ";
     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
       if (I != MBB.succ_begin())

Added: llvm/trunk/test/CodeGen/MIR/X86/unreachable_block.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unreachable_block.ll?rev=313685&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unreachable_block.ll (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/unreachable_block.ll Tue Sep 19 14:55:51 2017
@@ -0,0 +1,48 @@
+; RUN: llc -mtriple x86_64-- -stop-before peephole-opt -o %t.mir %s
+; RUN: llc -mtriple x86_64-- -run-pass none %t.mir -verify-machineinstrs -o - | FileCheck %s
+
+; Unreachable blocks in the machine instr representation are these
+; weird empty blocks with no successors.
+; The MIR printer used to not print empty lists of successors. However,
+; the MIR parser now treats non-printed list of successors as "please
+; guess it for me". As a result, the parser tries to guess the list of
+; successors and given the block is empty, just assumes it falls through
+; the next block.
+;
+; The following test case used to fail the verifier because the false
+; path ended up falling through split.true and now, the definition of
+; %v does not dominate all its uses.
+; Indeed, we go from the following CFG:
+;          entry
+;         /      \
+;    true (def)   false
+;        |
+;  split.true (use)
+;
+; To this one:
+;          entry
+;         /      \
+;    true (def)   false
+;        |        /  <-- invalid edge
+;  split.true (use)
+;
+; Because of the invalid edge, we get the "def does not
+; dominate all uses" error.
+;
+; CHECK-LABEL: name: foo
+; CHECK-LABEL: bb.{{[0-9]+}}.false:
+; CHECK-NEXT: successors:
+; CHECK-NOT: %bb.{{[0-9]+}}.split.true
+; CHECK-LABEL: bb.{{[0-9]+}}.split.true:
+define void @foo(i32* %bar) {
+  br i1 undef, label %true, label %false
+true:
+  %v = load i32, i32* %bar
+  br label %split.true
+false:
+  unreachable
+split.true:
+  %vInc = add i32 %v, 1
+  store i32 %vInc, i32* %bar
+  ret void
+}