[PATCH] D37974: [AArch64] Add V8_2aOps feature to Cortex-A55 and 75

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL313535: [AArch64] Add V8_2aOps feature to Cortex-A55 and 75 (authored by sam_parker).

Changed prior to commit:
  https://reviews.llvm.org/D37974?vs=115636&id=115650#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D37974

Files:
  llvm/trunk/lib/Target/AArch64/AArch64.td
  llvm/trunk/test/MC/AArch64/armv8.1a-lse.s
  llvm/trunk/test/MC/AArch64/crc.s
  llvm/trunk/test/MC/AArch64/ras-extension.s


Index: llvm/trunk/test/MC/AArch64/ras-extension.s
===================================================================
--- llvm/trunk/test/MC/AArch64/ras-extension.s
+++ llvm/trunk/test/MC/AArch64/ras-extension.s
@@ -1,4 +1,6 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ras < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s | FileCheck %s
 
   esb
 // CHECK: esb                             // encoding: [0x1f,0x22,0x03,0xd5]
Index: llvm/trunk/test/MC/AArch64/armv8.1a-lse.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.1a-lse.s
+++ llvm/trunk/test/MC/AArch64/armv8.1a-lse.s
@@ -1,5 +1,9 @@
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a,+lse -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
   .text
 
   cas w0, w1, [x2]
Index: llvm/trunk/test/MC/AArch64/crc.s
===================================================================
--- llvm/trunk/test/MC/AArch64/crc.s
+++ llvm/trunk/test/MC/AArch64/crc.s
@@ -1,6 +1,11 @@
 // RUN: llvm-mc -triple aarch64-- -mattr=+crc %s 2>&1 |\
 // RUN:   FileCheck %s --check-prefix=CRC
 
+// RUN: llvm-mc -triple aarch64-- -mcpu=cortex-a55 %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=CRC
+// RUN: llvm-mc -triple aarch64-- -mcpu=cortex-a75 %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=CRC
+
 // RUN: not llvm-mc -triple aarch64-- %s 2>&1 |\
 // RUN:   FileCheck %s --check-prefix=NOCRC
 // RUN: not llvm-mc -triple aarch64-- -mcpu=cyclone %s 2>&1 |\
Index: llvm/trunk/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td
+++ llvm/trunk/lib/Target/AArch64/AArch64.td
@@ -215,6 +215,7 @@
 
 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
                                    "Cortex-A55 ARM processors", [
+                                   HasV8_2aOps,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,
@@ -262,6 +263,7 @@
 
 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
                                    "Cortex-A75 ARM processors", [
+                                   HasV8_2aOps,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureFuseAES,


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