[PATCH] D37885: [x86] Bring back the MOVZX64rr* pseudo instructions so that they can be coalesced using X86InstrInfo::isCoalescableExtInstr

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

The InstrEmitter and the peephole pass both know how to use TTI->isCoalescableExtInstr to coalesce subregister accesses around MOVZX/MOVSX instructions since the lower bits are not altered. Unfortunately, they don't understand SUBREG_TO_REG  MOV32rr/MOVZX32rr16/MOVZX32rr8 we currently emit for zero extending to 64-bits.

This patch reintroduces pseudo instructions that we can recognize and handle in isCoalescableExtInst. These pseudo instructions used to exist, but were removed in r182921 in favor of SUBREG_TO_REG. I've modified the pseudos relative to the original versions by making them true pseudos which get converted after register allocation instead of in X86MCInstLower. I didn't add back the memory versions because we only care about register->register for this. We may need to teach load foldMemoryOperand about these things too, but I don't have a test case for that right now.

I think this broke what the tail-dup-merge-loop-headers.ll was trying to test. But the test case was a complicated case that the comments say bugpoint wasn't able to reduce very well so I have no idea how I could reconstruct it.


https://reviews.llvm.org/D37885

Files:
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86FixupSetCC.cpp
  lib/Target/X86/X86InstrCompiler.td
  lib/Target/X86/X86InstrExtension.td
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
  test/CodeGen/X86/MergeConsecutiveStores.ll
  test/CodeGen/X86/mul-i1024.ll
  test/CodeGen/X86/mul-i512.ll
  test/CodeGen/X86/musttail-varargs.ll
  test/CodeGen/X86/pr32340.ll
  test/CodeGen/X86/pr32345.ll
  test/CodeGen/X86/tail-dup-merge-loop-headers.ll

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