[PATCH] D37592: [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Normal loads are usually folded by isel patterns
Stack reloads created by the register allocator are folded using the load folding tables. Since these loads don't exist during isel we can't fold them there.
The peephole pass can also fold loads using the loading fold tables. At one point in time this was definitely weaker than the isel mechanism even ignoring the missing instructions in the isel table. I'm not sure what the status is now.

In this case I'd really like to be able to write an isel pattern for this instruction but I can't because there's no way to check the relationship of the two immediates. So I'm supplying custom code at the time of isel. If we were able to write the isel pattern we'd fold the load at that time. So I'm folding the load manually so that it happens during isel like it would if I could write the pattern. This is similar to what we do for integer MUL and DIV instructions that we also can't handle with isel patterns and do manually.


https://reviews.llvm.org/D37592