[PATCH] D37669: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

[jina via Phabricator via llvm-commits]

jina.nahias updated this revision to Diff 114593.
jina.nahias added a comment.

reduce the code lines in /lib/IR/AutoUpgrade.cpp


https://reviews.llvm.org/D37669

Files:
  lib/IR/AutoUpgrade.cpp


Index: lib/IR/AutoUpgrade.cpp
===================================================================
--- lib/IR/AutoUpgrade.cpp
+++ lib/IR/AutoUpgrade.cpp
@@ -1015,15 +1015,9 @@
                          Name.startswith("avx512.mask.pbroadcast.w.gpr") ||
                          Name.startswith("avx512.mask.pbroadcast.d.gpr") ||
                          Name.startswith("avx512.mask.pbroadcast.q.gpr"))) {
-      uint32_t ZeroIndex = 0;
-      Type *VT = CI->getArgOperand(1)->getType();
-      Type *VTZero = VectorType::get(Type::getInt32Ty(CI->getContext()),
-                                     VT->getVectorNumElements());
-      Value *ZeroinItializer = llvm::Constant::getNullValue(VTZero);
-      Rep = UndefValue::get(VT);
-      Rep = Builder.CreateInsertElement(Rep, CI->getArgOperand(0), ZeroIndex);
-      Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(VT),
-                                        ZeroinItializer);
+      unsigned NumElts =
+          CI->getArgOperand(1)->getType()->getVectorNumElements();
+      Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0));
       Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
                           CI->getArgOperand(1));
     } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) {


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