[PATCH] D37294: [X86][Skylake] Adding the scheduling information for the SkylakeClient target

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber updated this revision to Diff 114572.
gadi.haber added a comment.

Updated after the following changes:

1. modifying 3 Codegen tests to use the -mattr flag instead of the -mcpu flags.
2. removing remaining AVX512 instructions for mask registers manipulations in X86SchedSkylake.td
3. Changed the load latency from 4 cycles in HSW to 5 cycles.
4. Better regrouping some of the instructions in X86SchedSkylake.td


Repository:
  rL LLVM

https://reviews.llvm.org/D37294

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86Schedule.td
  test/CodeGen/X86/aes-schedule.ll
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/avx2-schedule.ll
  test/CodeGen/X86/bmi2-schedule.ll
  test/CodeGen/X86/f16c-schedule.ll
  test/CodeGen/X86/recip-fastmath.ll
  test/CodeGen/X86/recip-fastmath2.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse3-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/ssse3-schedule.ll

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