[llvm] r312908 - [ARM] Enable the use of SVC anywhere in an IT block

[Andre Vieira via llvm-commits]

Author: avieira
Date: Mon Sep 11 04:11:17 2017
New Revision: 312908

URL: http://llvm.org/viewvc/llvm-project?rev=312908&view=rev
Log:
[ARM] Enable the use of SVC anywhere in an IT block

Differential Revision: https://reviews.llvm.org/D37374

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=312908&r1=312907&r2=312908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 11 04:11:17 2017
@@ -8717,9 +8717,10 @@ template <> inline bool IsCPSRDead<MCIns
 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
 
-  // All branch & call instructions terminate IT blocks.
-  if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
-      MCID.isBranch() || MCID.isIndirectBranch())
+  // All branch & call instructions terminate IT blocks with the exception of
+  // SVC.
+  if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
+      MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
     return true;
 
   // Any arithmetic instruction which writes to the PC also terminates the IT

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=312908&r1=312907&r2=312908&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Sep 11 04:11:17 2017
@@ -3113,12 +3113,18 @@ _func:
         svceq #255
         it ne
         swine #33
+        itt eq
+        svceq #0
+        svceq #1
 
 @ CHECK: svc	#0                      @ encoding: [0x00,0xdf]
 @ CHECK: it	eq                      @ encoding: [0x08,0xbf]
 @ CHECK: svceq	#255                    @ encoding: [0xff,0xdf]
 @ CHECK: it	ne                      @ encoding: [0x18,0xbf]
 @ CHECK: svcne	#33                     @ encoding: [0x21,0xdf]
+@ CHECK: itt    eq                      @ encoding: [0x04,0xbf]
+@ CHECK: svceq  #0                      @ encoding: [0x00,0xdf]
+@ CHECK: svceq  #1                      @ encoding: [0x01,0xdf]
 
 
 @------------------------------------------------------------------------------