[PATCH] D37592: [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel

[Ayman Musa via Phabricator via llvm-commits]

aymanmus added inline comments.


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2129
+// See if this is an (X >> C1) & C2 that we can match to BEXTR/BEXTRI.
+bool X86DAGToDAGISel::matchBEXTRFromAnd(SDNode *Node) {
+  MVT NVT = Node->getSimpleValueType(0);
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Maybe add an assert to guarantee an 'AND' Node.


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2190
+  SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+  if (tryFoldLoad(Node, Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+    SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, New, Input.getOperand(0) };
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Why do you manually handle the memory folding here instead of letting the regular mechanism take care of that?


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2272
   case ISD::XOR: {
+
     // For operations of the form (x << C1) op C2, check if we can use a smaller
----------------
remove extra line


https://reviews.llvm.org/D37592