[llvm] r312720 - [mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFC
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 7 05:54:26 PDT 2017
Author: atanasyan
Date: Thu Sep 7 05:54:26 2017
New Revision: 312720
URL: http://llvm.org/viewvc/llvm-project?rev=312720&view=rev
Log:
[mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFC
This change converts the `MipsAsmBackend` constructor to the "standard"
form. It makes possible to use `RegisterMCAsmBackend` for the backends
registrations. Now we pass `Triple` instance to the `MipsAsmBackend`
ctor and deduce all required options like endianness and bitness from
the triple. We still need to implement explicit ABI checking for
providing correct options to backends.
Differential revision: https://reviews.llvm.org/D37519
Modified:
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=312720&r1=312719&r2=312720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Thu Sep 7 05:54:26 2017
@@ -211,8 +211,7 @@ static unsigned adjustFixupValue(const M
MCObjectWriter *
MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
- return createMipsELFObjectWriter(OS,
- MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
+ return createMipsELFObjectWriter(OS, TheTriple);
}
// Little-endian fixup data byte ordering:
@@ -474,35 +473,3 @@ bool MipsAsmBackend::writeNopData(uint64
OW->WriteZeros(Count);
return true;
}
-
-// MCAsmBackend
-MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
- /*Is64Bit*/ false);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
- /*Is64Bit*/ false);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
- /*Is64Bit*/ true);
-}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=312720&r1=312719&r2=312720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Thu Sep 7 05:54:26 2017
@@ -23,18 +23,18 @@ namespace llvm {
class MCAssembler;
struct MCFixupKindInfo;
-class Target;
class MCObjectWriter;
+class MCRegisterInfo;
+class Target;
class MipsAsmBackend : public MCAsmBackend {
- Triple::OSType OSType;
+ Triple TheTriple;
bool IsLittle; // Big or little endian
- bool Is64Bit; // 32 or 64 bit words
public:
- MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
- bool Is64Bit)
- : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
+ MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
+ StringRef CPU)
+ : TheTriple(TT), IsLittle(TT.isLittleEndian()) {}
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=312720&r1=312719&r2=312720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Thu Sep 7 05:54:26 2017
@@ -55,7 +55,7 @@ raw_ostream &operator<<(raw_ostream &OS,
class MipsELFObjectWriter : public MCELFObjectTargetWriter {
public:
- MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI, bool _isN64,
+ MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool IsN64,
bool IsLittleEndian);
~MipsELFObjectWriter() override = default;
@@ -209,11 +209,11 @@ static void dumpRelocs(const char *Prefi
}
#endif
-MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI,
- bool _isN64, bool IsLittleEndian)
- : MCELFObjectTargetWriter(_is64Bit, OSABI, ELF::EM_MIPS,
- /*HasRelocationAddend*/ _isN64,
- /*IsN64*/ _isN64) {}
+MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI,
+ bool HasRelocationAddend, bool IsN64,
+ bool IsLittleEndian)
+ : MCELFObjectTargetWriter(IsN64, OSABI, ELF::EM_MIPS, HasRelocationAddend,
+ IsN64) {}
unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
const MCValue &Target,
@@ -657,10 +657,13 @@ bool MipsELFObjectWriter::needsRelocateW
}
MCObjectWriter *llvm::createMipsELFObjectWriter(raw_pwrite_stream &OS,
- uint8_t OSABI,
- bool IsLittleEndian,
- bool Is64Bit) {
- MCELFObjectTargetWriter *MOTW =
- new MipsELFObjectWriter(Is64Bit, OSABI, Is64Bit, IsLittleEndian);
- return createELFObjectWriter(MOTW, OS, IsLittleEndian);
+ const Triple &TT) {
+ uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+ // FIXME: We need to check an actual ABI. mips64/mips64el do not
+ // always imply the N64 ABI and RELA relocation's format.
+ bool IsN64 = TT.isArch64Bit();
+ bool HasRelocationAddend = IsN64;
+ auto *MOTW = new MipsELFObjectWriter(OSABI, HasRelocationAddend, IsN64,
+ TT.isLittleEndian());
+ return createELFObjectWriter(MOTW, OS, TT.isLittleEndian());
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=312720&r1=312719&r2=312720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Thu Sep 7 05:54:26 2017
@@ -13,6 +13,7 @@
#include "MipsMCTargetDesc.h"
#include "InstPrinter/MipsInstPrinter.h"
+#include "MipsAsmBackend.h"
#include "MipsELFStreamer.h"
#include "MipsMCAsmInfo.h"
#include "MipsMCNaCl.h"
@@ -180,6 +181,9 @@ extern "C" void LLVMInitializeMipsTarget
TargetRegistry::RegisterObjectTargetStreamer(
*T, createMipsObjectTargetStreamer);
+
+ // Register the asm backend.
+ RegisterMCAsmBackend<MipsAsmBackend> Y(*T);
}
// Register the MC Code Emitter
@@ -188,14 +192,4 @@ extern "C" void LLVMInitializeMipsTarget
for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
-
- // Register the asm backend.
- TargetRegistry::RegisterMCAsmBackend(getTheMipsTarget(),
- createMipsAsmBackendEB32);
- TargetRegistry::RegisterMCAsmBackend(getTheMipselTarget(),
- createMipsAsmBackendEL32);
- TargetRegistry::RegisterMCAsmBackend(getTheMips64Target(),
- createMipsAsmBackendEB64);
- TargetRegistry::RegisterMCAsmBackend(getTheMips64elTarget(),
- createMipsAsmBackendEL64);
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h?rev=312720&r1=312719&r2=312720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Thu Sep 7 05:54:26 2017
@@ -43,25 +43,8 @@ MCCodeEmitter *createMipsMCCodeEmitterEL
const MCRegisterInfo &MRI,
MCContext &Ctx);
-MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-
-MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
- bool IsLittleEndian, bool Is64Bit);
+MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS,
+ const Triple &TT);
namespace MIPS_MC {
StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
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