[llvm] r312654 - [IfConversion] Remove kill flags from common instructions as well

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 6 10:57:13 PDT 2017


Author: kparzysz
Date: Wed Sep  6 10:57:13 2017
New Revision: 312654

URL: http://llvm.org/viewvc/llvm-project?rev=312654&view=rev
Log:
[IfConversion] Remove kill flags from common instructions as well

When if-converting a diamond, two separate blocks will be placed back
to back to form a straight line code. To ensure correctness of the
liveness information, any registers that are live in the second block
should not be killed in the first block, even if they were in the
original code.
Additionally, when the two blocks share common instructions at the
beginning, these instructions will not be duplicated, but only placed
once, before both of the blocks. Since the function "isIdenticalTo"
(as used here) ignores kill flags, the common initial code in one
block may have a kill flag for a register that is live in the other
block.
Because the code that removes kill flags only runs for the non-common
parts of the predicated blocks, a kill flag mismatch in the common
code could still lead to a live register being killed prematurely.

Added:
    llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir
Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=312654&r1=312653&r2=312654&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Sep  6 10:57:13 2017
@@ -1764,6 +1764,12 @@ bool IfConverter::IfConvertDiamondCommon
       Redefs.stepForward(MI, Dummy);
     }
   }
+  // Kill flags in the true block for registers living into the false block
+  // must be removed. This should be done before extracting the common
+  // instructions from the beginning of the MBB1, since these instructions
+  // can actually differ between MBB1 and MBB2 in terms of <kill> flags.
+  RemoveKills(MBB1.begin(), MBB1.end(), DontKill, *TRI);
+
   BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1);
   MBB2.erase(MBB2.begin(), DI2);
 
@@ -1788,10 +1794,6 @@ bool IfConverter::IfConvertDiamondCommon
   }
   MBB1.erase(DI1, MBB1.end());
 
-  // Kill flags in the true block for registers living into the false block
-  // must be removed.
-  RemoveKills(MBB1.begin(), MBB1.end(), DontKill, *TRI);
-
   DI2 = BBI2->BB->end();
   // The branches have been checked to match. Skip over the branch in the false
   // block so that we don't try to predicate it.

Added: llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir?rev=312654&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir Wed Sep  6 10:57:13 2017
@@ -0,0 +1,34 @@
+# RUN: llc -march=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s
+
+# CHECK: %r26 = A2_tfr %r1
+# CHECK: S2_pstorerhf_io undef %p0, undef %r0, 0, killed %r1
+
+---
+name:            foo
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %r0, %r1
+      J2_jumpf undef %p0, %bb.2, implicit-def %pc
+
+  bb.1:
+    successors: %bb.3
+    liveins: %r1
+      ; This <kill> flag should be cleared. It didn't use to be, because
+      ; this instruction is treated as a duplicate of the corresponding
+      ; instruction from the "false" block bb.2. Clearing of the <kill>
+      ; flags was limited to the non-common part of the "true" block.
+      %r26 = A2_tfr killed %r1
+      J2_jump %bb.3, implicit-def %pc
+
+  bb.2:
+    successors: %bb.3
+    liveins: %r1
+      %r26 = A2_tfr %r1
+      S2_storerh_io undef %r0, 0, killed %r1
+      J2_jump %bb.3, implicit-def %pc
+
+  bb.3:
+    liveins: %r26
+...




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