[llvm] r312502 - [x86] add/regenerate complete checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 4 14:43:32 PDT 2017
Author: spatel
Date: Mon Sep 4 14:43:32 2017
New Revision: 312502
URL: http://llvm.org/viewvc/llvm-project?rev=312502&view=rev
Log:
[x86] add/regenerate complete checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/2012-12-1-merge-multiple.ll
llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash.ll
llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash2.ll
Modified: llvm/trunk/test/CodeGen/X86/2012-12-1-merge-multiple.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-12-1-merge-multiple.ll?rev=312502&r1=312501&r2=312502&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-12-1-merge-multiple.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-12-1-merge-multiple.ll Mon Sep 4 14:43:32 2017
@@ -1,12 +1,14 @@
-; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
-; CHECK: multiple_stores_on_chain
-; CHECK: movabsq
-; CHECK: movq
-; CHECK: movabsq
-; CHECK: movq
-; CHECK: ret
define void @multiple_stores_on_chain(i16 * %A) {
+; CHECK-LABEL: multiple_stores_on_chain:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: movabsq $844433520132096, %rax # imm = 0x3000200010000
+; CHECK-NEXT: movq %rax, (%rdi)
+; CHECK-NEXT: movabsq $1970350607106052, %rax # imm = 0x7000600050004
+; CHECK-NEXT: movq %rax, 8(%rdi)
+; CHECK-NEXT: retq
entry:
%a0 = getelementptr inbounds i16, i16* %A, i64 0
%a1 = getelementptr inbounds i16, i16* %A, i64 1
Modified: llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash.ll?rev=312502&r1=312501&r2=312502&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash.ll Mon Sep 4 14:43:32 2017
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mcpu=core-avx-i -mtriple=i386-unknown-linux-gnu -mattr=+avx,+popcnt,+cmov
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=core-avx-i -mtriple=i386-unknown-linux-gnu -mattr=+avx,+popcnt,+cmov | FileCheck %s
; Make sure that we don't introduce illegal build_vector dag nodes
; when trying to fold a sign_extend of a constant build_vector.
@@ -6,6 +7,12 @@
; due to an illegal build_vector of type MVT::v4i64.
define <4 x i64> @foo(<4 x i64> %A) {
+; CHECK-LABEL: foo:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmovdqa %xmm1, %xmm1
+; CHECK-NEXT: vandps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: retl
%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i64> %A, <4 x i64><i64 undef, i64 undef, i64 0, i64 0>
ret <4 x i64> %1
}
Modified: llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash2.ll?rev=312502&r1=312501&r2=312502&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-vector-sext-crash2.ll Mon Sep 4 14:43:32 2017
@@ -1,96 +1,155 @@
-; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -check-prefix=X64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s -check-prefix=X64
; DAGCombiner crashes during sext folding
define <2 x i256> @test_sext1() {
+; X32-LABEL: test_sext1:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl $-1, 60(%eax)
+; X32-NEXT: movl $-1, 56(%eax)
+; X32-NEXT: movl $-1, 52(%eax)
+; X32-NEXT: movl $-1, 48(%eax)
+; X32-NEXT: movl $-1, 44(%eax)
+; X32-NEXT: movl $-1, 40(%eax)
+; X32-NEXT: movl $-1, 36(%eax)
+; X32-NEXT: movl $-99, 32(%eax)
+; X32-NEXT: movl $0, 28(%eax)
+; X32-NEXT: movl $0, 24(%eax)
+; X32-NEXT: movl $0, 20(%eax)
+; X32-NEXT: movl $0, 16(%eax)
+; X32-NEXT: movl $0, 12(%eax)
+; X32-NEXT: movl $0, 8(%eax)
+; X32-NEXT: movl $0, 4(%eax)
+; X32-NEXT: movl $0, (%eax)
+; X32-NEXT: retl $4
+;
+; X64-LABEL: test_sext1:
+; X64: # BB#0:
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: movaps %xmm0, 16(%rdi)
+; X64-NEXT: movaps %xmm0, (%rdi)
+; X64-NEXT: movq $-1, 56(%rdi)
+; X64-NEXT: movq $-1, 48(%rdi)
+; X64-NEXT: movq $-1, 40(%rdi)
+; X64-NEXT: movq $-99, 32(%rdi)
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: retq
%Se = sext <2 x i8> <i8 -100, i8 -99> to <2 x i256>
%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
ret <2 x i256> %Shuff
-
- ; X64-LABEL: test_sext1
- ; X64: movq $-1
- ; X64-NEXT: movq $-1
- ; X64-NEXT: movq $-1
- ; X64-NEXT: movq $-99
-
- ; X32-LABEL: test_sext1
- ; X32: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-99
}
define <2 x i256> @test_sext2() {
+; X32-LABEL: test_sext2:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl $-1, 60(%eax)
+; X32-NEXT: movl $-1, 56(%eax)
+; X32-NEXT: movl $-1, 52(%eax)
+; X32-NEXT: movl $-1, 48(%eax)
+; X32-NEXT: movl $-1, 44(%eax)
+; X32-NEXT: movl $-1, 40(%eax)
+; X32-NEXT: movl $-1, 36(%eax)
+; X32-NEXT: movl $-1999, 32(%eax) # imm = 0xF831
+; X32-NEXT: movl $0, 28(%eax)
+; X32-NEXT: movl $0, 24(%eax)
+; X32-NEXT: movl $0, 20(%eax)
+; X32-NEXT: movl $0, 16(%eax)
+; X32-NEXT: movl $0, 12(%eax)
+; X32-NEXT: movl $0, 8(%eax)
+; X32-NEXT: movl $0, 4(%eax)
+; X32-NEXT: movl $0, (%eax)
+; X32-NEXT: retl $4
+;
+; X64-LABEL: test_sext2:
+; X64: # BB#0:
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: movaps %xmm0, 16(%rdi)
+; X64-NEXT: movaps %xmm0, (%rdi)
+; X64-NEXT: movq $-1, 56(%rdi)
+; X64-NEXT: movq $-1, 48(%rdi)
+; X64-NEXT: movq $-1, 40(%rdi)
+; X64-NEXT: movq $-1999, 32(%rdi) # imm = 0xF831
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: retq
%Se = sext <2 x i128> <i128 -2000, i128 -1999> to <2 x i256>
%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
ret <2 x i256> %Shuff
-
- ; X64-LABEL: test_sext2
- ; X64: movq $-1
- ; X64-NEXT: movq $-1
- ; X64-NEXT: movq $-1
- ; X64-NEXT: movq $-1999
-
- ; X32-LABEL: test_sext2
- ; X32: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1999
}
define <2 x i256> @test_zext1() {
+; X32-LABEL: test_zext1:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl $0, 60(%eax)
+; X32-NEXT: movl $0, 56(%eax)
+; X32-NEXT: movl $0, 52(%eax)
+; X32-NEXT: movl $0, 48(%eax)
+; X32-NEXT: movl $0, 44(%eax)
+; X32-NEXT: movl $0, 40(%eax)
+; X32-NEXT: movl $0, 36(%eax)
+; X32-NEXT: movl $254, 32(%eax)
+; X32-NEXT: movl $0, 28(%eax)
+; X32-NEXT: movl $0, 24(%eax)
+; X32-NEXT: movl $0, 20(%eax)
+; X32-NEXT: movl $0, 16(%eax)
+; X32-NEXT: movl $0, 12(%eax)
+; X32-NEXT: movl $0, 8(%eax)
+; X32-NEXT: movl $0, 4(%eax)
+; X32-NEXT: movl $0, (%eax)
+; X32-NEXT: retl $4
+;
+; X64-LABEL: test_zext1:
+; X64: # BB#0:
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: movaps %xmm0, 48(%rdi)
+; X64-NEXT: movaps %xmm0, 16(%rdi)
+; X64-NEXT: movaps %xmm0, (%rdi)
+; X64-NEXT: movq $0, 40(%rdi)
+; X64-NEXT: movq $254, 32(%rdi)
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: retq
%Se = zext <2 x i8> <i8 -1, i8 -2> to <2 x i256>
%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
ret <2 x i256> %Shuff
-
- ; X64-LABEL: test_zext1
- ; X64: xorps %xmm0, %xmm0
- ; X64: movaps %xmm0
- ; X64: movaps %xmm0
- ; X64: movaps %xmm0
- ; X64-NEXT: movq $0
- ; X64-NEXT: movq $254
-
- ; X32-LABEL: test_zext1
- ; X32: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $254
}
define <2 x i256> @test_zext2() {
+; X32-LABEL: test_zext2:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl $0, 60(%eax)
+; X32-NEXT: movl $0, 56(%eax)
+; X32-NEXT: movl $0, 52(%eax)
+; X32-NEXT: movl $0, 48(%eax)
+; X32-NEXT: movl $-1, 44(%eax)
+; X32-NEXT: movl $-1, 40(%eax)
+; X32-NEXT: movl $-1, 36(%eax)
+; X32-NEXT: movl $-2, 32(%eax)
+; X32-NEXT: movl $0, 28(%eax)
+; X32-NEXT: movl $0, 24(%eax)
+; X32-NEXT: movl $0, 20(%eax)
+; X32-NEXT: movl $0, 16(%eax)
+; X32-NEXT: movl $0, 12(%eax)
+; X32-NEXT: movl $0, 8(%eax)
+; X32-NEXT: movl $0, 4(%eax)
+; X32-NEXT: movl $0, (%eax)
+; X32-NEXT: retl $4
+;
+; X64-LABEL: test_zext2:
+; X64: # BB#0:
+; X64-NEXT: xorps %xmm0, %xmm0
+; X64-NEXT: movaps %xmm0, 48(%rdi)
+; X64-NEXT: movaps %xmm0, 16(%rdi)
+; X64-NEXT: movaps %xmm0, (%rdi)
+; X64-NEXT: movq $-1, 40(%rdi)
+; X64-NEXT: movq $-2, 32(%rdi)
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: retq
%Se = zext <2 x i128> <i128 -1, i128 -2> to <2 x i256>
%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
ret <2 x i256> %Shuff
-
- ; X64-LABEL: test_zext2
- ; X64: xorps %xmm0, %xmm0
- ; X64-NEXT: movaps %xmm0
- ; X64-NEXT: movaps %xmm0
- ; X64-NEXT: movaps %xmm0
- ; X64-NEXT: movq $-1
- ; X64-NEXT: movq $-2
-
- ; X32-LABEL: test_zext2
- ; X32: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $0
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-1
- ; X32-NEXT: movl $-2
}
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