[PATCH] D36193: AMDGPU: IMPLICIT_DEFs do not contribute to wait states

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL312337: AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states (authored by nha).

Changed prior to commit:
  https://reviews.llvm.org/D36193?vs=109232&id=113550#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36193

Files:
  llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/trunk/test/CodeGen/AMDGPU/hazard.mir


Index: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -218,12 +218,17 @@
 
 int GCNHazardRecognizer::getWaitStatesSince(
     function_ref<bool(MachineInstr *)> IsHazard) {
-  int WaitStates = -1;
+  int WaitStates = 0;
   for (MachineInstr *MI : EmittedInstrs) {
+    if (MI) {
+      if (IsHazard(MI))
+        return WaitStates;
+
+      unsigned Opcode = MI->getOpcode();
+      if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF)
+        continue;
+    }
     ++WaitStates;
-    if (!MI || !IsHazard(MI))
-      continue;
-    return WaitStates;
   }
   return std::numeric_limits<int>::max();
 }
Index: llvm/trunk/test/CodeGen/AMDGPU/hazard.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hazard.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/hazard.mir
@@ -0,0 +1,31 @@
+# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+
+# GCN:    bb.0.entry:
+# GCN:      %m0 = S_MOV_B32
+# GFX9:     S_NOP 0
+# VI-NOT:   S_NOP_0
+# GCN:      V_INTERP_P1_F32
+
+---
+name:            hazard_implicit_def
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '%sgpr7', virtual-reg: '' }
+  - { reg: '%vgpr4', virtual-reg: '' }
+body:             |
+  bb.0.entry:
+    liveins: %sgpr7, %vgpr4
+
+    %m0 = S_MOV_B32 killed %sgpr7
+    %vgpr5 = IMPLICIT_DEF
+    %vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
+    SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
+
+...


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