[PATCH] D37320: [X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort.

We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code.

Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one.


https://reviews.llvm.org/D37320

Files:
  lib/Target/X86/X86FastISel.cpp
  test/CodeGen/X86/fast-isel-sext-zext.ll

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