[llvm] r312099 - [X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as well

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Aug 29 22:00:35 2017
New Revision: 312099

URL: http://llvm.org/viewvc/llvm-project?rev=312099&view=rev
Log:
[X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as well

Currently we start applying this on Haswell and newer. I don't believe anything changed in the Haswell architecture to make this the right cutoff point. The partial flag handling around this has been roughly the same since Sandybridge.

Differential Revision: https://reviews.llvm.org/D37250

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/test/CodeGen/X86/misched-fusion.ll
    llvm/trunk/test/CodeGen/X86/rdrand.ll

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=312099&r1=312098&r2=312099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Tue Aug 29 22:00:35 2017
@@ -528,6 +528,7 @@ def SNBFeatures : ProcessorFeatures<[],
   FeatureSlow3OpsLEA,
   FeatureFastScalarFSQRT,
   FeatureFastSHLDRotate,
+  FeatureSlowIncDec,
   FeatureMacroFusion
 ]>;
 
@@ -560,8 +561,7 @@ def HSWFeatures : ProcessorFeatures<IVBF
   FeatureERMSB,
   FeatureFMA,
   FeatureLZCNT,
-  FeatureMOVBE,
-  FeatureSlowIncDec
+  FeatureMOVBE
 ]>;
 
 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,

Modified: llvm/trunk/test/CodeGen/X86/misched-fusion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-fusion.ll?rev=312099&r1=312098&r2=312099&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/misched-fusion.ll (original)
+++ llvm/trunk/test/CodeGen/X86/misched-fusion.ll Tue Aug 29 22:00:35 2017
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx -disable-lsr -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx -mattr=-slow-incdec -disable-lsr -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s
 
 ; Verify that TEST+JE are scheduled together.
 ; CHECK: test_je

Modified: llvm/trunk/test/CodeGen/X86/rdrand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rdrand.ll?rev=312099&r1=312098&r2=312099&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rdrand.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rdrand.ll Tue Aug 29 22:00:35 2017
@@ -93,7 +93,7 @@ define void @loop(i32* %p, i32 %n) nounw
 ; X86-NEXT:    rdrandl %edx
 ; X86-NEXT:    movl %edx, (%ecx)
 ; X86-NEXT:    leal 4(%ecx), %ecx
-; X86-NEXT:    decl %eax
+; X86-NEXT:    addl $-1, %eax
 ; X86-NEXT:    jne .LBB3_2
 ; X86-NEXT:  .LBB3_3: # %while.end
 ; X86-NEXT:    retl
@@ -108,7 +108,7 @@ define void @loop(i32* %p, i32 %n) nounw
 ; X64-NEXT:    rdrandl %eax
 ; X64-NEXT:    movl %eax, (%rdi)
 ; X64-NEXT:    leaq 4(%rdi), %rdi
-; X64-NEXT:    decl %esi
+; X64-NEXT:    addl $-1, %esi
 ; X64-NEXT:    jne .LBB3_1
 ; X64-NEXT:  .LBB3_2: # %while.end
 ; X64-NEXT:    retq