[llvm] r311853 - [DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111)

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Sun Aug 27 10:29:30 2017
New Revision: 311853

URL: http://llvm.org/viewvc/llvm-project?rev=311853&view=rev
Log:
[DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111)

As noted in the FIXME, this could be improved more, but this is the smallest fix
that helps:
https://bugs.llvm.org/show_bug.cgi?id=34111

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/haddsub.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=311853&r1=311852&r2=311853&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Aug 27 10:29:30 2017
@@ -8863,12 +8863,15 @@ SDValue DAGCombiner::visitBITCAST(SDNode
       if (Op.getOpcode() == ISD::BITCAST &&
           Op.getOperand(0).getValueType() == VT)
         return SDValue(Op.getOperand(0));
-      if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
+      if (Op.isUndef() || ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
           ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
         return DAG.getBitcast(VT, Op);
       return SDValue();
     };
 
+    // FIXME: If either input vector is bitcast, try to convert the shuffle to
+    // the result type of this bitcast. This would eliminate at least one
+    // bitcast. See the transform in InstCombine.
     SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
     SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
     if (!(SV0 && SV1))

Modified: llvm/trunk/test/CodeGen/X86/haddsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub.ll?rev=311853&r1=311852&r2=311853&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/haddsub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/haddsub.ll Sun Aug 27 10:29:30 2017
@@ -401,18 +401,13 @@ define <2 x float> @haddps_v2f32(<4 x fl
 define <4 x float> @PR34111(<4 x float> %a) {
 ; SSE3-LABEL: PR34111:
 ; SSE3:       # BB#0:
-; SSE3-NEXT:    movaps %xmm0, %xmm1
-; SSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; SSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE3-NEXT:    addps %xmm1, %xmm0
+; SSE3-NEXT:    haddps %xmm0, %xmm0
 ; SSE3-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE3-NEXT:    retq
 ;
 ; AVX-LABEL: PR34111:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[0,2,2,3]
-; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; AVX-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vhaddps %xmm0, %xmm0, %xmm0
 ; AVX-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX-NEXT:    retq
   %a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>