[lld] r311712 - [MIPS] Merge multiple functions for writing relocation result into the single one. NFC
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 14:57:03 PDT 2017
Author: atanasyan
Date: Thu Aug 24 14:57:03 2017
New Revision: 311712
URL: http://llvm.org/viewvc/llvm-project?rev=311712&view=rev
Log:
[MIPS] Merge multiple functions for writing relocation result into the single one. NFC
Modified:
lld/trunk/ELF/Arch/Mips.cpp
Modified: lld/trunk/ELF/Arch/Mips.cpp
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Arch/Mips.cpp?rev=311712&r1=311711&r2=311712&view=diff
==============================================================================
--- lld/trunk/ELF/Arch/Mips.cpp (original)
+++ lld/trunk/ELF/Arch/Mips.cpp Thu Aug 24 14:57:03 2017
@@ -143,36 +143,11 @@ void MIPS<ELFT>::writeGotPlt(uint8_t *Bu
}
template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
-static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
- uint32_t Mask = 0xffffffff >> (32 - BSIZE);
- uint32_t Instr = read32<E>(Loc);
- if (SHIFT > 0)
- checkAlignment<(1 << SHIFT)>(Loc, V, Type);
- checkInt<BSIZE + SHIFT>(Loc, V, Type);
- write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
-}
-
-template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) {
+static void writeRelocation(uint8_t *Loc, uint32_t Type, uint64_t V) {
uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
+ uint32_t Mask = 0xffffffff >> (32 - BSIZE);
+ uint32_t Data = (Instr & ~Mask) | ((V >> SHIFT) & Mask);
+ write32<E>(Loc, Data);
}
template <class ELFT> static bool isMipsR6() {
@@ -201,9 +176,9 @@ template <class ELFT> void MIPS<ELFT>::w
write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
uint64_t GotPlt = InX::GotPlt->getVA();
- writeMipsHi16<E>(Buf, GotPlt);
- writeMipsLo16<E>(Buf + 4, GotPlt);
- writeMipsLo16<E>(Buf + 8, GotPlt);
+ writeRelocation<E, 16, 16>(Buf, R_MIPS_HI16, GotPlt + 0x8000);
+ writeRelocation<E, 16, 0>(Buf + 4, R_MIPS_LO16, GotPlt);
+ writeRelocation<E, 16, 0>(Buf + 8, R_MIPS_LO16, GotPlt);
}
template <class ELFT>
@@ -216,9 +191,9 @@ void MIPS<ELFT>::writePlt(uint8_t *Buf,
// jr $25
write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
- writeMipsHi16<E>(Buf, GotPltEntryAddr);
- writeMipsLo16<E>(Buf + 4, GotPltEntryAddr);
- writeMipsLo16<E>(Buf + 12, GotPltEntryAddr);
+ writeRelocation<E, 16, 16>(Buf, R_MIPS_HI16, GotPltEntryAddr + 0x8000);
+ writeRelocation<E, 16, 0>(Buf + 4, R_MIPS_LO16, GotPltEntryAddr);
+ writeRelocation<E, 16, 0>(Buf + 12, R_MIPS_LO16, GotPltEntryAddr);
}
template <class ELFT>
@@ -337,17 +312,17 @@ void MIPS<ELFT>::relocateOne(uint8_t *Lo
write64<E>(Loc, Val);
break;
case R_MIPS_26:
- write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
+ writeRelocation<E, 26, 2>(Loc, Type, Val);
break;
case R_MIPS_GOT16:
// The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
// is updated addend (not a GOT index). In that case write high 16 bits
// to store a correct addend value.
if (Config->Relocatable)
- writeMipsHi16<E>(Loc, Val);
+ writeRelocation<E, 16, 16>(Loc, Type, Val + 0x8000);
else {
checkInt<16>(Loc, Val, Type);
- writeMipsLo16<E>(Loc, Val);
+ writeRelocation<E, 16, 0>(Loc, Type, Val);
}
break;
case R_MIPS_GOT_DISP:
@@ -366,7 +341,7 @@ void MIPS<ELFT>::relocateOne(uint8_t *Lo
case R_MIPS_TLS_DTPREL_LO16:
case R_MIPS_TLS_GOTTPREL:
case R_MIPS_TLS_TPREL_LO16:
- writeMipsLo16<E>(Loc, Val);
+ writeRelocation<E, 16, 0>(Loc, Type, Val);
break;
case R_MIPS_CALL_HI16:
case R_MIPS_GOT_HI16:
@@ -374,31 +349,39 @@ void MIPS<ELFT>::relocateOne(uint8_t *Lo
case R_MIPS_PCHI16:
case R_MIPS_TLS_DTPREL_HI16:
case R_MIPS_TLS_TPREL_HI16:
- writeMipsHi16<E>(Loc, Val);
+ writeRelocation<E, 16, 16>(Loc, Type, Val + 0x8000);
break;
case R_MIPS_HIGHER:
- writeMipsHigher<E>(Loc, Val);
+ writeRelocation<E, 16, 32>(Loc, Type, Val + 0x80008000);
break;
case R_MIPS_HIGHEST:
- writeMipsHighest<E>(Loc, Val);
+ writeRelocation<E, 16, 48>(Loc, Type, Val + 0x800080008000);
break;
case R_MIPS_JALR:
// Ignore this optimization relocation for now
break;
case R_MIPS_PC16:
- applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
+ checkAlignment<4>(Loc, Val, Type);
+ checkInt<18>(Loc, Val, Type);
+ writeRelocation<E, 16, 2>(Loc, Type, Val);
break;
case R_MIPS_PC19_S2:
- applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
+ checkAlignment<4>(Loc, Val, Type);
+ checkInt<21>(Loc, Val, Type);
+ writeRelocation<E, 19, 2>(Loc, Type, Val);
break;
case R_MIPS_PC21_S2:
- applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
+ checkAlignment<4>(Loc, Val, Type);
+ checkInt<23>(Loc, Val, Type);
+ writeRelocation<E, 21, 2>(Loc, Type, Val);
break;
case R_MIPS_PC26_S2:
- applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
+ checkAlignment<4>(Loc, Val, Type);
+ checkInt<28>(Loc, Val, Type);
+ writeRelocation<E, 26, 2>(Loc, Type, Val);
break;
case R_MIPS_PC32:
- applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
+ writeRelocation<E, 32, 0>(Loc, Type, Val);
break;
default:
error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
More information about the llvm-commits
mailing list