[PATCH] D37096: [x86] Fix an amazing goof in the handling of sub, or, and xor lowering.

[Chandler Carruth via Phabricator via llvm-commits]

chandlerc created this revision.
Herald added subscribers: mcrosier, sanjoy.

The comment for this code indicated that it should work similar to our
handling of add lowering above: if we see uses of an instruction other
than flag usage and store usage, it tries to avoid the specialized
X86ISD::* nodes that are designed for flag+op modeling.

Problem is, only the add case actually did this. In all the other cases,
the logic was incomplete and inverted. Any time the value was used by
a store, we bailed on the specialized X86ISD node.

Turns out, we have a *ton* of patterns designed around these nodes. We
should actually form them. I fixed the code to match what we do for add,
and it has quite a positive effect just within some of our test cases.
The only thing close to a regression I see is using:

  notl %r
  testl %r, %r

instead of:

  xorl -1, %r

But we can add a pattern or something to fold that back out. The
improvements seem more than worth this.

Unless I'm missing any context here? I just made what seemed like
a "doh!" bug fix, and got ... much more in the way of generated code
changes than I was expecting....


https://reviews.llvm.org/D37096

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/atomic-minmax-i6432.ll
  test/CodeGen/X86/atomic128.ll
  test/CodeGen/X86/cmov.ll
  test/CodeGen/X86/cmp.ll
  test/CodeGen/X86/select.ll
  test/CodeGen/X86/tbm_patterns.ll

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