[llvm] r311572 - [AVX512] Don't create SHRUNKBLEND SDNodes for 512-bit vectors

[Hans Wennborg via llvm-commits]

Merged to 5.0 in r311593.

On Wed, Aug 23, 2017 at 9:41 AM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Wed Aug 23 09:41:02 2017
> New Revision: 311572
>
> URL: http://llvm.org/viewvc/llvm-project?rev=311572&view=rev
> Log:
> [AVX512] Don't create SHRUNKBLEND SDNodes for 512-bit vectors
>
> There are no 512-bit blend instructions so we shouldn't create SHRUNKBLEND for them.
>
> On a side note, it looks like there may be a missed opportunity for constant folding TESTM when LHS and RHS are equal.
>
> This fixes PR34139.
>
> Differential Revision: https://reviews.llvm.org/D36992
>
> Added:
>     llvm/trunk/test/CodeGen/X86/pr34139.ll
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=311572&r1=311571&r2=311572&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 23 09:41:02 2017
> @@ -30628,6 +30628,9 @@ static SDValue combineSelect(SDNode *N,
>      // Byte blends are only available in AVX2
>      if (VT == MVT::v32i8 && !Subtarget.hasAVX2())
>        return SDValue();
> +    // There are no 512-bit blend instructions that use sign bits.
> +    if (VT.is512BitVector())
> +      return SDValue();
>
>      assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
>      APInt DemandedMask(APInt::getSignMask(BitWidth));
>
> Added: llvm/trunk/test/CodeGen/X86/pr34139.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr34139.ll?rev=311572&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pr34139.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/pr34139.ll Wed Aug 23 09:41:02 2017
> @@ -0,0 +1,24 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=knl | FileCheck %s
> +
> +define void @f_f(<16 x double>* %ptr) {
> +; CHECK-LABEL: f_f:
> +; CHECK:       # BB#0:
> +; CHECK-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
> +; CHECK-NEXT:    vmovdqa %xmm0, (%rax)
> +; CHECK-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
> +; CHECK-NEXT:    vmovapd (%rdi), %zmm1
> +; CHECK-NEXT:    vmovapd 64(%rdi), %zmm2
> +; CHECK-NEXT:    vptestmq %zmm0, %zmm0, %k1
> +; CHECK-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
> +; CHECK-NEXT:    vmovapd %zmm0, %zmm2 {%k1}
> +; CHECK-NEXT:    vmovapd %zmm2, 64(%rdi)
> +; CHECK-NEXT:    vmovapd %zmm1, (%rdi)
> +  store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* undef
> +  %load_mask8.i.i.i = load <16 x i8>, <16 x i8>* undef
> +  %v.i.i.i.i = load <16 x double>, <16 x double>* %ptr
> +  %mask_vec_i1.i.i.i51.i.i = icmp ne <16 x i8> %load_mask8.i.i.i, zeroinitializer
> +  %v1.i.i.i.i = select <16 x i1> %mask_vec_i1.i.i.i51.i.i, <16 x double> undef, <16 x double> %v.i.i.i.i
> +  store <16 x double> %v1.i.i.i.i, <16 x double>* %ptr
> +  unreachable
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits