[PATCH] D36944: [InstCombine] Fix a weakness in canEvaluateZExtd around 'and' instructions

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311343: [InstCombine] Fix a weakness in canEvaluateZExtd around 'and' instructions (authored by ctopper).

Changed prior to commit:
  https://reviews.llvm.org/D36944?vs=111913&id=111992#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36944

Files:
  llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
  llvm/trunk/test/Transforms/InstCombine/cast.ll


Index: llvm/trunk/test/Transforms/InstCombine/cast.ll
===================================================================
--- llvm/trunk/test/Transforms/InstCombine/cast.ll
+++ llvm/trunk/test/Transforms/InstCombine/cast.ll
@@ -1588,15 +1588,12 @@
 }
 
 ; We should be able to remove the zext and trunc here.
-; TODO: This is currently blocked because we don't realize the 'and' has cleared the extra bits that would be shifted in widening the lshr.
 define i32 @test95(i32 %x) {
 ; CHECK-LABEL: @test95(
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 6
-; CHECK-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = or i8 [[TMP3]], 40
-; CHECK-NEXT:    [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
+; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = trunc i32 %x to i8
   %2 = lshr i8 %1, 6
Index: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
===================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -950,8 +950,13 @@
       unsigned VSize = V->getType()->getScalarSizeInBits();
       if (IC.MaskedValueIsZero(I->getOperand(1),
                                APInt::getHighBitsSet(VSize, BitsToClear),
-                               0, CxtI))
+                               0, CxtI)) {
+        // If this is an And instruction and all of the BitsToClear are
+        // known to be zero we can reset BitsToClear.
+        if (Opc == Instruction::And)
+          BitsToClear = 0;
         return true;
+      }
     }
 
     // Otherwise, we don't know how to analyze this BitsToClear case yet.


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